Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V 1  voltage to the first wiring, applies V 2  voltage lower than V 1  to a selected cell gate of the selected cell transistor, applies V 3  voltage not higher than V 1  and higher than V 2  to a non-selected cell gate of the first memory transistors, applies V 1  or V 4  voltage not higher than V 1  and not lower than V 3  to the first select gate, and applies V 2  or V 4  voltage higher than V 2  and not higher than V 3  to the second wiring or sets the second wiring in a floating state.

More than one reissue application has been filed for the reissue of U.S.Pat. No. 8,320,182. The reissue applications are the present reissuecontinuation application and Ser. No. 14/335,639 (parent application).The present application claims benefit of priority under 35 U.S.C. § 120of application Ser. No. 14/335,639.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-202063, filed on Sep. 1,2009; the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Field

Embodiments of the invention relate generally to a nonvolatilesemiconductor memory device.

2. Background Art

Conventional flash memories are based on collective erase and selectivewrite operation. In this operation, memory cells in no need of rewritingdata are also rewritten. Hence, the reliability may be degraded with theincreasing number of times of rewriting data. Further, a rewriting speedis decreased because memory cells in no need of rewriting data torewrite are rewritten.

In conventional memories, a plurality of memory cells are formed in acommon semiconductor layer on a substrate and have a common channel,which makes it difficult to implement selective erasure. In thiscontext, JP-A 2006-190820 (Kokai) discloses a method for selectiveerasure by using holes resulting from band-to-band tunneling current.However, this method is prone to degradation in reliability because alocal electric field is applied to memory cells. Furthermore, theoperation is unstable because of the narrow driving margin between theselected cell and the non-selected cell.

It is desired to realize a memory in which only the memory cell in needof rewriting data can be selectively and stably rewritten so that thelifetime of memory cells can be extended. Further, it is possible torewrite data at high speed by selective erasure.

SUMMARY

According to an aspect of the invention, there is provided a nonvolatilesemiconductor memory device including: a memory unit; and a controlunit, the memory unit including a first memory string, a first wiring, asecond memory string, and a second wiring, the first memory stringincluding a first memory cell group and a first select transistor, thefirst memory cell group including a plurality of first memorytransistors connected in series, each of the plurality of first memorytransistors including a channel formed in a first semiconductor layer,including a first control gate, and allowing data of the each of theplurality of first memory transistors to be electrically rewritten, thefirst select transistor being provided on one end side of the firstmemory cell group, including a channel formed in the first semiconductorlayer, and including a first select gate, the first wiring beingconnected to the first semiconductor layer on a side of the first selecttransistor opposite to the first memory cell group, the second memorystring including a second memory cell group and a second selecttransistor, the second memory cell group including a plurality of secondmemory transistors connected in series, each of the plurality of secondmemory transistors including a channel formed in a second semiconductorlayer electrically isolated from the first semiconductor layer,including a control gate electrically connected to the first controlgate, and allowing data of the each of the plurality of second memorytransistors to be electrically rewritten, the second select transistorbeing provided on one end side of the second memory cell group,including a channel formed in the second semiconductor layer, andincluding a select gate connected to the first select gate, the secondwiring being connected to the second semiconductor layer on a side ofthe second select transistor opposite to the second memory cell group,in a selective erase operation for performing at least one of injectionof a hole into a charge retention layer of a selected cell transistor inthe selective erase operation of the first memory transistors andextraction of an electron from the charge retention layer of theselected cell transistor in the selective erase operation, the controlunit being configured to: apply a first voltage to the first wiring,apply a second voltage lower than the first voltage to a selected cellgate of the first control gate of the selected cell transistor in theselective erase operation, apply a third voltage not higher than thefirst voltage and higher than the second voltage to a non-selected cellgate in the selective erase operation of the first control gate of thefirst memory transistors other than the selected cell transistor in theselective erase operation, apply the first voltage or a fourth voltagenot higher than the first voltage and not lower than the third voltageto the first select gate, and apply the second voltage or a fifthvoltage higher than the second voltage and not higher than the thirdvoltage to the second wiring or set the second wiring in a floatingstate.

According to another aspect of the invention, there is provided anonvolatile semiconductor memory device including: a memory unit; and acontrol unit, the memory unit including a first memory string, a firstwiring, a first other wiring, and a first base wiring, the first memorystring including a first memory cell group, a first other memory cellgroup, a first select transistor, a first other select transistor, and afirst connecting portion transistor, the first memory cell groupincluding a plurality of first memory transistors connected in series,each of the plurality of first memory transistors including a channelformed in a first semiconductor layer provided in contact with a firstbase semiconductor layer, including a first control gate, and allowingdata of the each of the plurality of first memory transistors to beelectrically rewritten, the first select transistor being provided onone end side of the first memory cell group, including a channel formedin the first semiconductor layer, and including a first select gate, thefirst other select transistor being provided on a side of the firstmemory cell group opposite to the first select transistor, including achannel formed in the first semiconductor layer, and including a firstother select gate, the first connecting portion transistor beingprovided between the first memory cell group and the first other selecttransistor, including a channel formed in the first semiconductor layer,and including a first connecting portion gate, the first other memorycell group being provided between the first other select transistor andthe first connecting portion transistor and including a plurality offirst other memory transistors connected in series, each of theplurality of first other memory transistors including a channel formedin the first semiconductor layer, including a first other control gate,and allowing data of the each of the plurality of first other memorytransistors to be electrically rewritten, the first wiring beingconnected to the first semiconductor layer on a side of the first selecttransistor opposite to the first memory cell group, the first otherwiring being connected to the first semiconductor layer on a side of thefirst other select transistor opposite to the first other memory cellgroup, the first base wiring being connected to the first basesemiconductor layer, in a selective erase operation for performing atleast one of injection of a hole into a charge retention layer of aselected cell transistor in the selective erase operation of the firstmemory transistors and extraction of an electron from the chargeretention layer of the selected cell transistor in the selective eraseoperation, the control unit being configured to: apply a first voltageto the first wiring and the first other wiring or set the first wiringand the first other wiring in a floating state, apply a second voltagelower than the first voltage to a selected cell gate of the firstcontrol gate of the selected cell transistor in the selective eraseoperation, apply a third voltage lower than the first voltage and higherthan the second voltage to a non-selected cell gate in the selectiveerase operation of the first control gate of the first memorytransistors other than the selected cell transistor in the selectiveerase operation, apply the third voltage to the first other controlgate, apply a tenth voltage lower than the first voltage and higher thanthe second voltage to the first select gate and the first other selectgate, apply an eleventh voltage lower than the first voltage and higherthan the second voltage to the first connecting portion gate, and applythe first voltage to the first base wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic diagrams illustrating the configurationand operation of a nonvolatile semiconductor memory device according toa first embodiment;

FIG. 2 is a schematic perspective view illustrating the configuration ofa nonvolatile semiconductor memory device according to a first practicalexample;

FIG. 3 is a schematic cross-sectional view illustrating theconfiguration of the nonvolatile semiconductor memory device accordingto the first practical example;

FIG. 4 is a schematic partial cross-sectional view illustrating theconfiguration of the nonvolatile semiconductor memory device accordingto the first practical example;

FIG. 5 is a schematic diagram illustrating the configuration of anonvolatile semiconductor memory device according to a secondembodiment;

FIG. 6 is a table illustrating the operation of the nonvolatilesemiconductor memory device according to the second embodiment;

FIG. 7 is a schematic diagram illustrating the configuration of analternative nonvolatile semiconductor memory device according to thesecond embodiment;

FIG. 8 is a table illustrating the operation of the alternativenonvolatile semiconductor memory device according to the secondembodiment;

FIG. 9 is a schematic perspective view illustrating the configuration ofa nonvolatile semiconductor memory device according to a secondpractical example;

FIG. 10 is a schematic cross-sectional view illustrating theconfiguration of the nonvolatile semiconductor memory device accordingto the second practical example;

FIG. 11 is a schematic diagram illustrating the configuration of anonvolatile semiconductor memory device according to a third embodiment;

FIG. 12 is a table illustrating the operation of the nonvolatilesemiconductor memory device according to the third embodiment;

FIG. 13 is a schematic diagram illustrating the configuration of analternative nonvolatile semiconductor memory device according to thethird embodiment;

FIG. 14 is a table illustrating the operation of the alternativenonvolatile semiconductor memory device according to the thirdembodiment; and

FIG. 15 is a schematic perspective view illustrating the configurationof a nonvolatile semiconductor memory device according to a thirdpractical example.

DETAILED DESCRIPTION

Embodiments of the invention will now be described with reference to thedrawings.

The drawings are schematic or conceptual. The relationship between thethickness and the width of each portion, and the size ratio between theportions, for instance, are not necessarily identical to those inreality. Furthermore, the same portion may be shown with differentdimensions or ratios depending on the figures.

In the specification and drawings of the application, the same elementsas those described previously with reference to earlier figures arelabeled with like reference numerals, and the detailed descriptionthereof is omitted as appropriate.

First Embodiment

FIGS. 1A and 1B are schematic diagrams illustrating the configurationand operation of a nonvolatile semiconductor memory device according toa first embodiment.

More specifically, FIG. 1A is a circuit diagram illustrating theconfiguration of a nonvolatile semiconductor memory device 101, and FIG.1B is a table illustrating the operation of the nonvolatilesemiconductor memory device 101. In FIG. 1A, for clarity ofillustration, some wirings are not shown.

As shown in FIG. 1A, the nonvolatile semiconductor memory device 101according to this embodiment includes a memory unit MU and a controlunit CTU.

The memory unit MU includes a first memory string MCS1, a first wiringW11, a second memory string MCS2, and a second wiring W21.

In the following description, illustratively, a first bit line BL1 isused as the first wiring W11, and a second bit line BL2 is used as thesecond wiring W21.

The first memory string MCS1 includes a first memory cell group MCG1 anda first select transistor SGT11. In the following description, a firstdrain side select transistor SDT1 is illustratively used as the firstselect transistor SGT11.

The first memory cell group MCG1 includes a plurality of first memorytransistors MC1A (which are memory cells MC, such as first to fourthmemory cells MC1 to MC4) connected in series. Each of the plurality offirst memory transistors MC1A allows its data to be electricallyrewritten.

Each of the plurality of first memory transistors MC1A includes a firstsemiconductor layer SEM1. That is, the plurality of first memorytransistors MC1A include a channel formed in the first semiconductorlayer SEM1. Specifically, a source region, a drain region, and a channelregion (channel) of each of the plurality of first memory transistorsMC1A are provided in the first semiconductor layer SEM1. Each of theplurality of first memory transistors MC1A (first to fourth memory cellsMC1 to MC4) includes a first control gate CG1A (control gates CG1-1 toCG1-4).

The first drain side select transistor SDT1 is provided on one end sideof the first memory cell group MCG1. The first drain side selecttransistor SDT1 includes the same first semiconductor layer SEM1 as thefirst memory cell group MCG1. That is, the first drain side selecttransistor SDT1 includes a channel formed in the first semiconductorlayer SEM1. Specifically, a source region, a drain region, and a channelregion (channel) of the first drain side select transistor SDT1 areprovided in the first semiconductor layer SEM1. The first drain sideselect transistor SDT1 includes a first select gate SG11. In thefollowing description, a first drain side select gate SGD1 isillustratively used as the first select gate SG11.

The first bit line BL1 is connected to the first semiconductor layerSEM1 on the opposite side of the first drain side select transistor SDT1from the first memory cell group MCG1. The first bit line BL1 functionsas a bit line BL in the first memory string MCS1.

In the nonvolatile semiconductor memory device 101 of this example, thefirst memory string MCS1 further includes a first other selecttransistor SGT12. In the following description, a first source sideselect transistor SST1 is illustratively used as the first other selecttransistor SGT12.

The first source side select transistor SST1 is provided on the oppositeside of the first memory cell group MCG1 from the first drain sideselect transistor SDT1 and includes the first semiconductor layer SEM1.The first source side select transistor SST1 includes a first otherselect gate SG12. In the following description, a first source sideselect gate SGS1 is illustratively used as the first other select gateSG12.

The memory unit MU further includes a first other wiring W12. In thefollowing description, a first source line SL1 is illustratively used asthe first other wiring W12.

The first source line SL1 is connected to the first semiconductor layerSEM1 on the opposite side of the first source side select transistorSST1 from the first memory cell group MCG1. The first source line SL1functions as a source line SL in the first memory string MCS1.

On the other hand, the second memory string MCS2 includes a secondmemory cell group MCG2 and a second select transistor SGT21. In thefollowing description, a second drain side select transistor SDT2 isillustratively used as the second select transistor SGT21.

The second memory cell group MCG2 includes a plurality of second memorytransistors MC2A (which are memory cells MC, such as fifth to eighthmemory cells MC5 to MC8) connected in series. Each of the plurality ofsecond memory transistors MC2A allows its data to be electricallyrewritten.

The plurality of second memory transistors MC2A include a secondsemiconductor layer SEM2 electrically isolated from the firstsemiconductor layer SEM1. That is, the plurality of second memorytransistors MC2A include a channel formed in the second semiconductorlayer SEM2. Specifically, a source region, a drain region, and a channelregion (channel) of each of the plurality of second memory transistorsMC2A are provided in the second semiconductor layer SEM2 separate fromthe first semiconductor layer SEM1. The respective control gates of thefifth to eighth memory cells MC5 to MC8 are commonly connected to thecontrol gates (first control gates CG1A, or control gates CG1-1 toCG1-4) of the first to fourth memory cells MC1 to MC4.

The second drain side select transistor SDT2 is provided on one end sideof the second memory cell group MCG2. The second drain side selecttransistor SDT2 includes the same second semiconductor layer SEM2 as thesecond memory cell group MCG2. That is, the second drain side selecttransistor SDT2 includes a channel formed in the second semiconductorlayer SEM2. Specifically, the source region, the drain region, and thechannel region (channel) of the second drain side select transistor SDT2are provided in the second semiconductor layer SEM2. The second drainside select transistor SDT2 includes a select gate connected to thefirst drain side select gate SGD1.

The second bit line BL2 is connected to the second semiconductor layerSEM2 on the opposite side of the second drain side select transistorSDT2 from the second memory cell group MCG2. The second bit line BL2functions as a bit line BL in the second memory string MCS2.

In the nonvolatile semiconductor memory device 101 of this example, thesecond memory string MCS2 further includes a second other selecttransistor SGT22. In the following description, a second source sideselect transistor SST2 is illustratively used as the second other selecttransistor SGT22.

The second source side select transistor SST2 is provided on theopposite side of the second memory cell group MCG2 from the second drainside select transistor SDT2 and includes the second semiconductor layerSEM2. The second source side select transistor SST2 includes a selectgate connected to the first source side select gate SGS1.

The memory unit MU further includes a second other wiring W22. In thefollowing description, a second source line SL2 is illustratively usedas the second other wiring W22.

The second source line SL2 is connected to the second semiconductorlayer SEM2 on the opposite side of the second source side selecttransistor SST2 from the second memory cell group MCG2. The secondsource line SL2 functions as a source line SL in the second memorystring MCS2.

In the foregoing, the number of first and second memory transistors MC1Aand MC2A is four for each. However, the number of first and secondmemory transistors MC1A and MC2A is arbitrary as long as it is more thanone for each.

The geometry of the first semiconductor layer SEM1 and the secondsemiconductor layer SEM2 is arbitrary as long as they are electricallyisolated from each other. For instance, the first and secondsemiconductor layers SEM1 and SEM2 are provided on a substrate (e.g.,silicon substrate) so as to align in the direction perpendicular to themajor surface of the substrate. Alternatively, the first and secondsemiconductor layers SEM1 and SEM2 may be an SOI (silicon on insulator)provided on a substrate. In this case, the first and secondsemiconductor layers SEM1 and SEM2 align in a plane parallel to themajor surface of the substrate.

The number of semiconductor layers is arbitrary as long as the first ton-th semiconductor layers are electrically isolated from each other,where n is any integer of two or more. The geometry (e.g., positionalrelation to the major surface of the substrate) of the first to n-thsemiconductor layer is arbitrary.

Furthermore, whether perpendicular or parallel to the major surface ofthe substrate, the first to n-th semiconductor layers are not limited tolinearly aligning in one direction but may be folded back in a “U-shape”or “W-shape”, for instance.

In the following description, the first and second semiconductor layersSEM1 and SEM2 illustratively align in one direction.

The control unit CTU controls the memory unit MU thus configured. InFIG. 1A, for clarity of illustration, the control unit CTU is connectedto the first drain side select gate SGD1 and the first bit line BL1.However, the control unit CTU is connected to various electrodes andwirings described above to control respective potentials (voltages).

Here, the erase operation in the nonvolatile semiconductor memory device101 is the operation for performing at least one of injection of holesinto the charge retention layer of the memory cell MC and extraction ofelectrons from the charge retention layer. Here, the charge retentionlayer is a layer for retaining charge in the memory cell MC andillustratively includes a charge storage layer made of an insulatinglayer and a floating electrode made of a conductive layer. The chargeretention layer is illustratively provided between the channel regionand the control gate (gate electrode) of the memory cell MC. A tunnelinsulating film is provided between the charge retention layer and thechannel region, and a block insulating film is provided between thecharge retention layer and the control gate.

(Selective Erase Operation ER)

In the following, a description is given of the operation of the controlunit CTU in selective erasure in the nonvolatile semiconductor memorydevice 101.

As shown in FIG. 1B, in the selective erase operation ER for performingat least one of injection of holes into the charge retention layer of aselected cell transistor CL1 (in this example, third memory cell MC3) ofthe first memory transistors MC1A (in this example, first to fourthmemory cells MC1 to MC4) and extraction of electrons from the chargeretention layer, the control unit CTU performs the following operation.

The control unit CTU applies a first voltage V1 to the first bit lineBL1. The first voltage V1 is illustratively a high voltage Vpp. The highvoltage Vpp is illustratively set to 20 volts (V).

Furthermore, the control unit CTU applies a second voltage V2 lower thanthe first voltage V1 to the selected cell gate (control gate CG1-3) ofthe selected cell transistor CL1. The second voltage V2 isillustratively 0 volts (0 V, or ground potential, which may be areference potential).

Furthermore, the control unit CTU applies a third voltage V3 not higherthan the first voltage V1 and higher than the second voltage V2 to thenon-selected cell gates (in this example, control gate CG1-1, controlgate CG1-2, and control gate CG1-4) of the first memory transistors MC1A(in this example, first memory cell MC1, second memory cell MC2, andfourth memory cell MC4) other than the selected cell transistor CL1. Thethird voltage V3 is illustratively a medium voltage Vm between the highvoltage Vpp and 0 V. The medium voltage Vm is illustratively set to 10V.

Furthermore, the control unit CTU applies the first voltage V1 (highvoltage Vpp) or a fourth voltage V4 not higher than the first voltage V1and not lower than the third voltage V3 to the first drain side selectgate SGD1 of the first drain side select transistor SDT1. The fourthvoltage V4 is illustratively the medium voltage Vm. In the followingdescription, the medium voltage Vm is illustratively used as the fourthvoltage V4.

Furthermore, the control unit CTU applies a fifth voltage V5 higher thanthe second voltage V2 and not higher than the third voltage V3 to thesecond bit line BL2 or sets the second bit line BL2 in a floating stateOPN. The fifth voltage V5 is illustratively a low voltage Vcc, which isa voltage higher than the second voltage V2 (0 V) and not higher thanthe third voltage V3 (medium voltage Vm). The low voltage Vcc isillustratively set to 3 V. Alternatively, the control unit CTU may applythe second voltage V2 (0 V) to the second bit line BL2.

In this example, the first source line SL1 is subjected to the firstvoltage V1 (high voltage Vpp), the low voltage Vcc, or the secondvoltage V2 (0 V), or the first source line SL1 is set in the floatingstate OPN. Furthermore, the first source side select gate SGS1 issubjected to the first voltage V1 (high voltage Vpp) or the fourthvoltage V4 (medium voltage Vm), which is equal to the voltage applied tothe first drain side select gate SGD1. Furthermore, the second sourceline SL2 is subjected to the second voltage (0 V) or the fifth voltageV5 (low voltage Vcc), which is equal to the voltage applied to thesecond bit line BL2.

Here, the same voltage as the voltage applied to the control gate(control gates CG1-1 to CG1-4) of the first memory string MCS1 isapplied to the control gate of each of the fifth to eighth memory cellsMC5 to MC8 of the second memory string MCS2 because the second memorystring MCS2 shares the control gate (control gates CG1-1 to CG1-4) withthe first memory string MCS1.

As described above, the selected cell gate (control gate CG1-3) of theselected cell transistor CL1 is subjected to 0 V, and the first bit lineBL1 and the first source line SL1 are subjected to the high voltage Vpp.This results in performing at least one of injection of holes into thecharge retention layer of the third memory cell MC3 and extraction ofelectrons from the charge retention layer. That is, the third memorycell MC3 is erased.

Furthermore, the voltage of the non-selected cell gates (control gateCG1-1, control gate CG1-2, and control gate CG1-4) of the first memorycell MC1, the second memory cell MC2, and the fourth memory cell MC4,which are not selected, is set to the third voltage V3 (medium voltageVm), and hence these cells are not erased.

In the second memory string MCS2 sharing control gates with the firstmemory string MCS1, the low voltage Vcc is applied to the second bitline BL2 and the second source line SL2. This suppresses erroneouswriting in the fifth, sixth, and eighth memory cells MC5, MC6, and MC8,and no erasure is performed on the seventh memory cell MC7 sharing thecontrol gate with the third memory cell MC3 because the applied voltageis low.

Setting to this potential relationship (voltage relationship) enablesonly the selected cell transistor CL1 to be erased, with the othermemory cells (non-selected cell transistors) prevented from erasure orerroneous writing. Selective erasure by this operation can improve theoperational reliability of the nonvolatile semiconductor memory device101. Further, it is possible to rewrite data at high speed by selectiveerasure.

In the case where the medium voltage Vm is a voltage low enough to avoidwriting, the second bit line BL2 and the second source line SL2 of thenon-selected second memory string MCS2 may be subjected to the secondvoltage V2 (0 V).

Furthermore, as shown in FIG. 1A, the memory unit MU further includes athird memory string MCS3.

The third memory string MCS3 includes a third memory cell group MCG3 anda third select transistor SGT31. In the following description, a thirddrain side select transistor SDT3 is illustratively used as the thirdselect transistor SGT31.

The third memory cell group MCG3 includes a plurality of third memorytransistors MC3A (which are memory cells MC, such as ninth to twelfthmemory cells MC9 to MC12) connected in series. Each of the plurality ofthird memory transistors MC3A allows its data to be electricallyrewritten.

Each of the plurality of third memory transistors MC3A includes a thirdsemiconductor layer SEM3. The third semiconductor layer SEM3 iselectrically isolated from the first semiconductor layer SEM1 and thesecond semiconductor layer SEM2. Each of the plurality of third memorytransistors MC3A includes a channel formed in the third semiconductorlayer SEM3. Each of the plurality of third memory transistors MC3A(ninth to twelfth memory cells MC9 to MC12) includes a second controlgate CG2A (control gates CG2-1 to CG2-4).

The third drain side select transistor SDT3 is provided on one end sideof the third memory cell group MCG3. The third drain side selecttransistor SDT3 includes the same third semiconductor layer SEM3 as thethird memory cell group MCG3. That is, the third drain side selecttransistor SDT3 includes a channel formed in the third semiconductorlayer SEM3. The third drain side select transistor SDT3 includes asecond select gate SG21. In the following description, a second drainside select gate SGD2 is illustratively used as the second select gateSG21.

Here, the second drain side select gate SGD2 is electrically isolatedfrom the first drain side select gate SGD1.

The first bit line BL1 is connected to the third semiconductor layerSEM3 on the opposite side of the third drain side select transistor SDT3from the third memory cell group MCG3. That is, one end of the firstsemiconductor layer SEM1 and one end of the third semiconductor layerSEM3 are commonly connected to the first bit line BL1.

The third memory string MCS3 further includes a third other selecttransistor SGT32 provided on the opposite side of the third memory cellgroup MCG3 from the third drain side select transistor SDT3. In thefollowing description, a third source side select transistor SST3 isillustratively used as the third other select transistor SGT32.

The third source side select transistor SST3 includes the thirdsemiconductor layer SEM3. The third source side select transistor SST3includes a second other select gate SG22. In the following description,a second source side select gate SGS2 is illustratively used as thesecond other select gate SG22.

The first source line SL1 is connected to the third semiconductor layerSEM3 on the opposite side of the third source side select transistorSST3 from the third memory cell group MCG3. That is, the first sourceline SL1 functions as a source line SL in the third memory string MCS3,as well as functioning as a source line SL in the first memory stringMCS1.

The control unit CTU further performs the following operation in theselective erase operation.

When the selected cell transistor CL1 of the first memory transistorsMC1A is selectively erased, the second control gates CG2A (control gatesCG2-1 to CG2-4) of the third memory transistors MC3A are subjected tothe third voltage V3 (medium voltage Vm) or a sixth voltage V6 lowerthan the third voltage V3. The sixth voltage V6 can be equal to thesecond voltage V2, such as 0 V.

Furthermore, the second drain side select gate SGD2 of the third drainside select transistor SDT3 is subjected to a seventh voltage V7 lowerthan the third voltage V3. The seventh voltage V7 can be equal to thesecond voltage V2, such as 0 V.

Here, the first bit line BL1 connected to the third semiconductor layerSEM3 of the third memory string MCS3 is subjected to the first voltageV1 (high voltage Vpp), and the second bit line BL2 is subjected to thefifth voltage V5 (low voltage Vcc) or 0 V or is set in the floatingstate OPN.

Hence, no data in the third memory transistors MC3A (ninth to twelfthmemory cells MC9 to MC12) of the third memory string MCS3 is rewritten.

Furthermore, as shown in FIG. 1A, the memory unit MU further includes afourth memory string MCS4.

The fourth memory string MCS4 includes a fourth memory cell group MCG4and a fourth select transistor SGT41. In the following description, afourth drain side select transistor SDT4 is illustratively used as thefourth select transistor SGT41.

The fourth memory cell group MCG4 includes a plurality of fourth memorytransistors MC4A (which are memory cells MC, such as thirteenth tosixteenth memory cells MC13 to MC16) connected in series. Each of theplurality of fourth memory transistors MC4A allows its data to beelectrically rewritten.

The plurality of fourth memory transistors MC4A (thirteenth to sixteenthmemory cells MC13 to MC16) include a fourth semiconductor layer SEM4.The fourth semiconductor layer SEM4 is electrically isolated from thefirst semiconductor layer SEM1, the second semiconductor layer SEM2, andthe third semiconductor layer SEM3. Each of the plurality of fourthmemory transistors MC4A includes a channel formed in the fourthsemiconductor layer SEM4. The respective control gates of the pluralityof fourth memory transistors MC4A (thirteenth to sixteenth memory cellsMC13 to MC16) are commonly connected to the second control gates CG2A(control gates CG2-1 to CG2-4) of the plurality of third memorytransistors MC3A (ninth to twelfth memory cells MC9 to MC12).

The fourth drain side select transistor SDT4 is provided on one end sideof the fourth memory cell group MCG4. The fourth drain side selecttransistor SDT4 includes the same fourth semiconductor layer SEM4 as thefourth memory cell group MCG4. That is, the fourth drain side selecttransistor SDT4 includes a channel formed in the fourth semiconductorlayer SEM4. The select gate of the fourth drain side select transistorSDT4 is connected to the second drain side select gate SGD2.

The second bit line BL2 is connected to the fourth semiconductor layerSEM4 on the opposite side of the fourth drain side select transistorSDT4 from the fourth memory cell group MCG4 (thirteenth to sixteenthmemory cells MC13 to MC16). That is, one end of the second semiconductorlayer SEM2 and one end of the fourth semiconductor layer SEM4 arecommonly connected to the second bit line BL2.

The fourth memory string MCS4 further includes a fourth other selecttransistor SGT42 provided on the opposite side of the fourth memory cellgroup MCG4 from the fourth drain side select transistor SDT4. In thefollowing description, a fourth source side select transistor SST4 isillustratively used as the fourth other select transistor SGT42.

The fourth source side select transistor SST4 includes the fourthsemiconductor layer SEM4. The select gate of the fourth source sideselect transistor SST4 is connected to the second source side selectgate SGS2.

The second source line SL2 is connected to the fourth semiconductorlayer SEM4 on the opposite side of the fourth source side selecttransistor SST4 from the fourth memory cell group MCG4. That is, thesecond source line SL2 functions as a source line SL in the fourthmemory string MCS4, as well as functioning as a source line SL in thesecond memory string MCS2.

Also in this fourth memory string MCS4, the control gates CG2-1 to CG2-4shared with the third memory string MCS3 are subjected to the sixthvoltage V6 (e.g., equal to the second voltage V2, or 0 V).

Furthermore, the select gate of the fourth drain side select transistorSDT4 is subjected to the seventh voltage V7 (e.g., equal to the secondvoltage V2, or 0 V) in common with the second drain side select gateSGD2. Here, the second bit line BL2 and the second source line SL2connected to the fourth semiconductor layer SEM4 of the fourth memorystring MCS4 are subjected to the fifth voltage V5 (low voltage Vcc) orthe second voltage V2 (0 V) or are set in the floating state OPN.

Hence, no data in the fourth memory transistors MC4A (thirteenth tosixteenth memory cells MC13 to MC16) of the fourth memory string MCS4 isrewritten.

Thus, only the selected cell transistor CL1 can be selectively erased,and the operational reliability of the nonvolatile semiconductor memorydevice 101 can be improved.

(Write Operation WR)

In the following, a description is given of the operation of the controlunit CTU in writing in the nonvolatile semiconductor memory device 101.Here, the write operation is the operation for performing at least oneof injection of electrons into the charge retention layer of the memorycell MC and extraction of holes from the charge retention layer.

In the write operation WR in a selected cell transistor CL1 (in thisexample, third memory cell MC3) of the first memory transistors MC1A (inthis example, first to fourth memory cells MC1 to MC4), the control unitCTU performs the following operation.

As shown in FIG. 1B, the control unit CTU applies a high voltage Vpp(e.g., the aforementioned first voltage V1) to the selected cell gate(CG1-3) of the selected cell transistor CL1.

Furthermore, the first bit line BL1 is subjected to 0 V (e.g., thesecond voltage V2 lower than the aforementioned first voltage V1).

The non-selected cell gates (control gate CG1-1, control gate CG1-2, andcontrol gate CG1-4) of the first memory transistors MC1A (first memorycell MC1, second memory cell MC2, and fourth memory cell MC4) other thanthe selected cell transistor CL1 are subjected to a voltage (e.g., lowvoltage Vcc) higher than the second voltage V2 and not higher than thethird voltage V3.

The first drain side select gate SGD1 of the first drain side selecttransistor SDT1 is subjected to a voltage (e.g., low voltage Vcc) higherthan the second voltage V2 and not higher than the third voltage V3.

The second bit line BL2 is subjected to a voltage (e.g., low voltageVcc) higher than the second voltage V2 and not higher than the thirdvoltage V3.

Thus, selective writing can be performed on the selected cell transistorCL1.

In the write operation WR, the control unit CTU can further perform thefollowing operation.

The first source line SL1 and the second source line SL2 are subjectedto 0 V (e.g., second voltage V2) or a low voltage Vcc, or the firstsource line SL1 and the second source line SL2 are set in the floatingstate OPN. Furthermore, the first source side select gate SGS1 of thefirst memory string MCS1 is also subjected to 0 V (e.g., second voltageV2).

Furthermore, in the write operation WR, the control unit CTU applies 0 V(e.g., a voltage lower than the aforementioned third voltage V3, such asthe second voltage V2) to the second control gates CG2A (control gatesCG2-1 to CG2-4) of the third memory transistors MC3A (ninth to twelfthmemory cells MC9 to MC12).

Furthermore, the second drain side select gate SGD2 of the third drainside select transistor SDT3 is subjected to a voltage lower than thethird voltage V3 (e.g., 0 V).

Here, the second source side select gate SGS2 of the third memory stringMCS3 is subjected to a voltage lower than the third voltage V3 (e.g., 0V).

Thus, erroneous writing in the third memory transistors MC3A (ninth totwelfth memory cells MC9 to MC12) of the third memory string MCS3 can beprevented.

In the fourth memory string MCS4, the select gate of the fourth drainside select transistor SDT4 is subjected to the same voltage (0 V) asthe second drain side select gate SGD2, and the select gate of thefourth source side select transistor SST4 is subjected to the samevoltage (0 V) as the second source side select gate SGS2. This canprevent erroneous writing in the fourth memory transistors MC4A(thirteenth to sixteenth memory cells MC13 to MC16) of the fourth memorystring MCS4.

(Read Operation RD)

In the following, a description is given of the operation of the controlunit CTU in the read operation RD in the nonvolatile semiconductormemory device 101.

As shown in FIG. 1B, the control unit CTU applies a reading bit linevoltage Ve not higher than the fifth voltage V5 (e.g., low voltage Vcc)and higher than the second voltage V2 (e.g., 0 V) to the first bit lineBL1. The reading bit line voltage Ve can illustratively be 1 V to 2 V.

The selected cell gate (control gate CG1-3) of the selected celltransistor CL1 is subjected to a sense voltage Vse varied between thelow voltage Vcc and the second voltage V2 (e.g., 0 V). The sense voltageVse is the voltage of an electrical signal for sensing the thresholdvoltage of the memory cell MC.

The non-selected cell gates (control gate CG1-1, control gate CG1-2, andcontrol gate CG1-4) of the first memory transistors MC1A (first memorycell MC1, second memory cell MC2, and fourth memory cell MC4) other thanthe selected cell transistor CL1 are subjected to the low voltage Vcc.

The first drain side select gate SGD1 of the first drain side selecttransistor SDT1 is subjected to the low voltage Vcc.

The second bit line BL2 is subjected to the second voltage V2 (e.g., 0V).

Thus, without erroneous writing in the memory cell MC of the firstmemory string MCS1, the data written in the memory cell MC can be read.

In the read operation RD, the control unit CTU can further perform thefollowing operation.

The first source line SL1 and the second source line SL2 are subjectedto the second voltage V2 (e.g., 0 V). Furthermore, the first source sideselect gate SGS1 of the first memory string MCS1 is illustrativelysubjected to the low voltage Vcc.

Furthermore, the control unit CTU illustratively applies 0 V (secondvoltage V2) to the second control gates CG2A (control gates CG2-1 toCG2-4) of the third memory transistors MC3A (ninth to twelfth memorycells MC9 to MC12).

Furthermore, the second drain side select gate SGD2 of the third drainside select transistor SDT3 is illustratively subjected to 0 V (secondvoltage V2).

Here, the second source side select gate SGS2 of the third memory stringMCS3 is also subjected to 0 V.

Thus, erroneous writing in the third memory transistors MC3A (ninth totwelfth memory cells MC9 to MC12) of the third memory string MCS3 can beprevented.

In the fourth memory string MCS4, the select gate of the fourth drainside select transistor SDT4 is subjected to 0 V, which is equal to thevoltage applied to the second drain side select gate SGD2, and theselect gate of the fourth source side select transistor SST4 issubjected to 0 V, which is equal to the voltage applied to the secondsource side select gate SGS2. This can prevent erroneous writing in thefourth memory transistors MC4A (thirteenth to sixteenth memory cellsMC13 to MC16) of the fourth memory string MCS4.

FIRST PRACTICAL EXAMPLE

In the following, a nonvolatile semiconductor memory device 110 of afirst practical example according to the first embodiment is described.

FIGS. 2, 3, and 4 are a schematic perspective view, a schematiccross-sectional view, and a schematic partial cross-sectional view,respectively, illustrating the configuration of the nonvolatilesemiconductor memory device according to the first practical example.

It is noted that for clarity of illustration, FIG. 2 shows only theconductive portions and omits the insulating portions.

As shown in FIGS. 2 and 3, the nonvolatile semiconductor memory device110 according to this practical example includes a memory unit MU and acontrol unit CTU. The memory unit MU and the control unit CTU areprovided on the major surface 11a of a substrate 11 illustratively madeof single crystal silicon. However, the control unit CTU may be providedon a substrate different from the substrate on which the memory unit MUis provided. In the following description, it is assumed that the memoryunit MU and the control unit CTU are provided on the same substrate(substrate 11).

On the substrate 11, for instance, a memory array region MR to beprovided with memory cells and a peripheral region PR illustrativelyprovided around the memory array region MR are defined. In theperipheral region PR, various peripheral region circuits PR1 areprovided on the substrate 11.

In the memory array region MR, a circuit unit CU is illustrativelyprovided on the substrate 11, and the memory unit MU is provided on thecircuit unit CU. It is noted that the circuit unit CU is provided asneeded and can be omitted. An interlayer insulating film 13aillustratively made of silicon oxide is provided between the circuitunit CU and the memory unit MU.

At least part of the control unit CTU, for instance, can illustrativelybe provided in at least one of the peripheral region circuit PR1 and thecircuit unit CU described above.

The memory unit MU includes a matrix memory cell unit MU1 including aplurality of memory transistors and a wiring connecting unit MU2 forconnecting wirings in the matrix memory cell unit MU1.

FIG. 2 illustrates the configuration of the matrix memory cell unit MU1.

With regard to the matrix memory cell unit MU1, FIG. 3 illustrates partof the A-A′ cross section of FIG. 2 and part of the B-B′ cross sectionof FIG. 2.

As shown in FIGS. 2 and 3, in the matrix memory cell unit MU1, amultilayer structure ML is provided on the major surface 11a of thesubstrate 11. The multilayer structure ML includes a plurality ofelectrode films WL and a plurality of interelectrode insulating films 14alternately stacked in the direction perpendicular to the major surface11a.

For convenience of description, the direction perpendicular to the majorsurface 11a of the substrate 11 is referred to as a Z-axis direction(first direction). Furthermore, one of the directions in the planeparallel to the major surface 11a is referred to as a Y-axis direction(second direction). Furthermore, the direction perpendicular to the Zaxis and the Y axis is referred to as an X-axis direction (thirddirection).

The stacking direction of the electrode films WL and the interelectrodeinsulating films 14 in the multilayer structure ML is the Z-axisdirection. That is, the electrode films WL and the interelectrodeinsulating films 14 are provided parallel to the major surface 11a. Theelectrode films WL are illustratively divided into erase blocks.

FIG. 4 illustrates the configuration of the matrix memory cell unit MU1,illustratively corresponding to part of the B-B′ cross section of FIG.3.

As shown in FIGS. 3 and 4, the memory unit MU of the nonvolatilesemiconductor memory device 110 includes the aforementioned multilayerstructure ML, a semiconductor pillar SP (first semiconductor pillar SP1)piercing the multilayer structure ML in the Z-axis direction, a memorylayer 48, an inner insulating film 42, and an outer insulating film 43.

The memory layer 48 is provided between each of the electrode films WLand the semiconductor pillar SP. The inner insulating film 42 isprovided between the memory layer 48 and the semiconductor pillar SP.The outer insulating film 43 is provided between each of the electrodefilms WL and the memory layer 48.

More specifically, the outer insulating film 43, the memory layer 48,and the inner insulating film 42 are formed in this order on the innerwall surface of the through hole TH piercing the multilayer structure MLin the Z-axis direction, and the remaining space is filled with asemiconductor to form the semiconductor pillar SP.

A memory cell MC is provided at the intersection between the electrodefilm WL of the multilayer structure ML and the semiconductor pillar SP.That is, memory transistors including the memory layer 48 are providedin a three-dimensional matrix, each at the intersection between theelectrode film WL and the semiconductor pillar SP. Each of the memorytransistors functions as a memory cell MC for storing data by storingcharge in the memory layer 48.

The semiconductor pillars SP constitute the first to fourthsemiconductor layers SEM1 to SEM4. The memory transistors formed in thesemiconductor pillars SP constitute the first to fourth memory cellgroups MCG1 to MCG4.

The inner insulating film 42 functions as a tunnel insulating film inthe memory transistor of the memory cell MC. On the other hand, theouter insulating film 43 functions as a block insulating film in thememory transistor of the memory cell MC. The interelectrode insulatingfilm 14 functions as an interlayer insulating film for insulating theelectrode films WL from each other.

The electrode film WL can be made of any conductive material, such asamorphous silicon or polysilicon provided with conductivity by impuritydoping, or can be made of metals and alloys. A prescribed electricalsignal is applied to the electrode film WL, which functions as a wordline of the nonvolatile semiconductor memory device 110.

The interelectrode insulating film 14, the inner insulating film 42, andthe outer insulating film 43 can illustratively be silicon oxide films.It is noted that the interelectrode insulating film 14, the innerinsulating film 42, and the outer insulating film 43 may be a monolayerfilm or a multilayer film.

The memory layer 48 can illustratively be a silicon nitride film andfunctions as a portion for storing data by storing or releasing chargeby an electric field applied between the semiconductor pillar SP and theelectrode film WL. The memory layer 48 may be a monolayer film or amultilayer film.

As described later, the interelectrode insulating film 14, the innerinsulating film 42, the memory layer 48, and the outer insulating film43 can be made of any material, not limited to the materials illustratedabove.

Although FIGS. 2 and 3 illustrate the case where the multilayerstructure ML includes four electrode films WL, the number of electrodefilms WL provided in the multilayer structure ML is arbitrary. In thefollowing description, it is assumed that the number of electrode filmsWL is four.

Furthermore, select gates SG are provided above and below the multilayerstructure ML.

More specifically, an upper select gate USG (illustratively serving as adrain side select gate) is provided above the multilayer structure ML,and a lower select gate LSG (illustratively serving as a source sideselect gate) is provided below the multilayer structure ML.

An upper select gate insulating film USGI illustratively made of siliconoxide is provided between the upper select gate USG and thesemiconductor pillar SP, and a lower select gate insulating film LSGIillustratively made of silicon oxide is provided between the lowerselect gate LSG and the semiconductor pillar SP.

Furthermore, a source line SL is provided below the lower select gateLSG. An interlayer insulating film 13a is provided below the source lineSL, and an interlayer insulating film 13b is provided between the sourceline SL and the lower select gate LSG.

The semiconductor pillar SP is connected to the source line SL below thelower select gate LSG and to a bit line BL above the upper select gateUSG.

The upper select gate USG and the lower select gate LSG are divided inthe Y-axis direction by an interlayer insulating film 17 and aninterlayer insulating film 13c, respectively, and shaped like stripsaligning along the X-axis direction.

The aforementioned select gates SG (upper select gate USG and lowerselect gate LSG) can be made of any conductive material, such aspolysilicon or amorphous silicon.

On the other hand, the bit line BL connected to the upper portion of thesemiconductor pillar SP and the source line SL connected to the lowerportion of the semiconductor pillar SP are shaped like strips aligningin the Y-axis direction.

In this case, the electrode film WL is a conductive film shaped like astrip aligning in the X-axis direction.

One of the upper select gates USG constitutes the first drain sideselect gate SGD1, and another of the upper select gates USG constitutesthe second drain side select gate SGD2. One of the lower select gatesLSG constitutes the first source side select gate SGS1, and another ofthe lower select gates LSG constitutes the second source side selectgate SGS2.

The first drain side select transistor SDT1 is provided at theintersection between the first semiconductor pillar SP1 and the firstdrain side select gate SGD1. The second drain side select transistorSDT2 is provided at the intersection between the second semiconductorpillar SP2 and the first drain side select gate SGD1. The third drainside select transistor SDT3 is provided at the intersection between thethird semiconductor pillar SP3 and the second drain side select gateSGD2. The fourth drain side select transistor SDT4 is provided at theintersection between the fourth semiconductor pillar SP4 and the seconddrain side select gate SGD2.

The first to fourth memory strings MCS1 to MCS4 are formed on the basisof the first to fourth semiconductor pillars SP1 to SP4.

In the nonvolatile semiconductor memory device 110, the control unit CTUperforms the operation illustrated in FIG. 1B. Thus, the selective eraseoperation ER can be performed, and the operational reliability can beimproved. Further, it is possible to rewrite data at high speed byselective erasure. Furthermore, the desired operation can be performedby the write operation WR and the read operation RD illustrated in FIG.1B.

In the nonvolatile semiconductor memory device 110, the semiconductorpillars SP are illustratively used as the first to fourth semiconductorlayers SEM1 to SEM4, which align in the direction perpendicular to themajor surface 11a of the substrate 11. However, the first to fourthsemiconductor layers SEM1 to SEM4 may illustratively be made of amaterial, such as SOI, aligning in the direction parallel to the majorsurface 11a of the substrate 11.

Second Embodiment

FIG. 5 is a schematic diagram illustrating the configuration of anonvolatile semiconductor memory device according to a secondembodiment. More specifically, FIG. 5 is a circuit diagram illustratingthe configuration of a nonvolatile semiconductor memory device 102. InFIG. 5, for clarity of illustration, some wirings are not shown.

FIG. 6 is a table illustrating the operation of the nonvolatilesemiconductor memory device according to the second embodiment.

As shown in FIG. 5, the nonvolatile semiconductor memory device 102according to this embodiment includes a connecting portion transistorCPT (first to fourth connecting portion transistors CPT1 to CPT4)halfway through each of the memory strings (first to fourth memorystrings MCS1 to MCS4) of the nonvolatile semiconductor memory device 101illustrated in FIG. 1. Each of the memory strings illustratively has afolded structure.

In the nonvolatile semiconductor memory device 102, the memory unit MUfurther includes a first source line SL1 and a second source line SL2 inaddition to the first memory string MCS1, the first bit line BL1, thesecond memory string MCS2, and the second bit line BL2.

In addition to the first memory cell group MCG1 and the first drain sideselect transistor SDT1, the first memory string MCS1 further includes afirst other memory cell group MCH1, a first source side selecttransistor SST1, and a first connecting portion transistor CPT1.

The first source side select transistor SST1 is provided on the oppositeside of the first memory cell group MCG1 from the first drain sideselect transistor SDT1. The first source side select transistor SST1includes a channel formed in the first semiconductor layer SEM1 andincludes a first source side select gate SGS1.

The first connecting portion transistor CPT1 is provided between thefirst memory cell group MCG1 and the first source side select transistorSST1, includes a channel formed in the first semiconductor layer SEM1,and includes a first connecting portion gate CPG1. In the followingdescription, a first back gate BG1 is illustratively used as the firstconnecting portion gate CPG1.

The first other memory cell group MCH1 is provided between the firstsource side select transistor SST1 and the first connecting portiontransistor CPT1 and includes a plurality of first other memorytransistors MC1B (memory cells MC) connected in series. As describedpreviously, the first memory cell group MCG1 includes the first memorytransistors MC1A (memory cells MC).

Each of the plurality of first other memory transistors MC1B includes achannel formed in the first semiconductor layer SEM1, includes a firstother control gate CG1B (control gates CG1/2-5 to CG1/2-8), and allowsits data to be electrically rewritten.

The first source line SL1 is connected to the first semiconductor layerSEM1 on the opposite side of the first source side select transistorSST1 from the first other memory cell group MCH1.

In this embodiment, the first control gates CG1A of the first memorycell group MCG1 are control gates CG0/1-1 to CG0/1-4.

Furthermore, in addition to the second memory cell group MCG2 and thesecond drain side select transistor SDT2, the second memory string MCS2further includes a second other memory cell group MCH2, a second sourceside select transistor SST2, and a second connecting portion transistorCPT2.

The second source side select transistor SST2 is provided on theopposite side of the second memory cell group MCG2 from the second drainside select transistor SDT2, includes a channel formed in the secondsemiconductor layer SEM2, and includes a second source side select gateSGS2.

The second connecting portion transistor CPT2 is provided between thesecond memory cell group MCG2 and the second source side selecttransistor SST2, includes a channel formed in the second semiconductorlayer SEM2, and includes a connecting portion gate electricallyconnected to the first back gate BG1.

The second other memory cell group MCH2 is provided between the secondsource side select transistor SST2 and the second connecting portiontransistor CPT2 and includes a plurality of second other memorytransistors MC2B (memory cells MC) connected in series. As describedpreviously, the second memory cell group MCG2 includes the second memorytransistors MC2A (memory cells MC).

Each of the plurality of second other memory transistors MC2B includes achannel formed in the second semiconductor layer SEM2, includes acontrol gate (second other control gate) electrically connected to thefirst other control gate CG1B, and allows its data to be electricallyrewritten.

The second source line SL2 is connected to the second semiconductorlayer SEM2 on the opposite side of the second source side selecttransistor SST2 from the second other memory cell group MCH2.

(Selective Erase Operation ER)

In the following, a description is given of the operation of the controlunit CTU in selective erasure in the nonvolatile semiconductor memorydevice 102.

In the selective erase operation ER on the charge retention layer of aselected cell transistor CL1 of the first memory transistors MC1A(memory cells MC belonging to the first memory cell group MCG1), thecontrol unit CTU performs the following operation. Here, this selectedcell transistor CL1 includes the control gate CG1-3.

As shown in FIG. 6, the control unit CTU applies a first voltage V1(high voltage Vpp, such as 20 V) to the first bit line BL1.

Furthermore, the selected cell gate (control gate CG0/1-3) of theselected cell transistor CL1 is subjected to a second voltage V2 (e.g.,0 V) lower than the first voltage V1.

The non-selected cell gates (control gate CG0/1-1, control gate CG0/1-2,and control gate CG0/1-4) of the first memory transistors MC1A otherthan the selected cell transistor CL1 are subjected to a third voltageV3 (a medium voltage Vm between the high voltage Vpp and 0 V, such as 10V) not higher than the first voltage V1 and higher than the secondvoltage V2.

The first drain side select gate SGD1 of the first drain side selecttransistor SDT1 is subjected to the first voltage V1 (high voltage Vpp)or a fourth voltage V4 (e.g., medium voltage Vm) not higher than thefirst voltage V1 and not lower than the third voltage V3.

The second bit line BL2 is subjected to a fifth voltage V5 (e.g., lowvoltage Vcc) higher than the second voltage V2 and not higher than thethird voltage V3. Here, as described previously, the second bit line BL2may be subjected to the second voltage V2 (e.g., 0 V).

The control unit CTU applies the fifth voltage V5 (low voltage Vcc) orthe second voltage (0 V) to the first source line SL1.

The first other control gate CG1B is subjected to the third voltage V3(medium voltage Vm).

The first source side select gate SGS1 is subjected to an eighth voltageV8 lower than the third voltage V3. The eighth voltage V8 canillustratively be the second voltage (0 V).

The first back gate BG1 is subjected to a ninth voltage V9 lower thanthe first voltage V1 (high voltage Vpp) and higher than the secondvoltage V2 (0 V). The ninth voltage V9 can illustratively be the mediumvoltage Vm.

The second source line SL2 is subjected to the second voltage V2 (0 V),the second control gates CG2A (control gates CG2/3-1 to CG2/3-4) issubjected to the sixth voltage V6 (0 V) or the third voltage V3 (mediumvoltage Vm), the second drain side select gate SGD2 is subjected to theeighth voltage V8, and the second source side select gate SGS2 issubjected to the eighth voltage V8.

Under this voltage relationship, the first drain side select transistorSDT1 is turned on, and the semiconductor pillar SP is charged. Thus,injection of positive charges or release of electrons, that is, erasure,is performed on the charge retention layer of the selected celltransistor CL1. That is, the threshold voltage of the selected celltransistor CL1 falls below 0 V.

Here, in the memory cell group (in this case, first memory cell groupMCG1) including the selected cell transistor CL1, the control gate ofthe non-selected memory cells is subjected to the medium voltage Vm(e.g., 10 V), and hence the applied electric field is low. Thus, thenon-selected memory cells are not erased.

On the other hand, in the memory strings sharing the control gate andselect gate with the selected cell transistor CL1 and being adjacent tothe memory string including the selected cell transistor CL1, becausethe second bit line BL2 is subjected to the fifth voltage V5 (lowvoltage Vcc, or 3 V) or the second voltage (0 V), the electric fieldapplied to the non-selected memory cell in these memory strings is low,and hence no erroneous writing occurs.

Furthermore, in the memory string to which the first bit line BL1 iscommonly connected, the select gate SG (second drain side select gateSGD2 and second source side select gate SGS2) is subjected to the eighthvoltage V8, or 0 V, thereby cut off. Thus, no erasure occurs.

The control gates (control gates CG1/2-5 to CG1/2-8 of the first othercontrol gate CG1B) shared with the first other memory cell group MCH1 ofthe selected memory string (first memory string MCS1) are subjected tothe medium voltage Vm (e.g., 10 V), and hence the applied electric fieldis low. Thus, no erroneous writing occurs in the memory cells MC (memorycells included in the second other memory cell group MCH2) associatedwith the control gates.

Furthermore, as shown in FIG. 5, like the first memory string MCS1, inaddition to the third memory cell group MCG3 and the third drain sideselect transistor SDT3, the third memory string MCS3 further includes athird other memory cell group MCH3, a third source side selecttransistor SST3, and a third connecting portion transistor CPT3.

Likewise, in addition to the fourth memory cell group MCG4 and thefourth drain side select transistor SDT4, the fourth memory string MCS4further includes a fourth other memory cell group MCH4, a fourth sourceside select transistor SST4, and a fourth connecting portion transistorCPT4.

The configuration of the third and fourth other memory cell groups MCH3and MCH4 and the third and fourth source side select transistors SST3and SST4 is the same as in the first and second memory strings MCS1 andMCS2, and hence the description thereof is omitted.

The control gates of the third and fourth memory cell groups MCG3 andMCG4 are connected to the first and second control gates CG1A and CG2Aof the first and second memory cell groups MCG1 and MCG2, respectively.

The control gates of the third and fourth other memory cell groups MCH3and MCH4 are connected to the first other control gate CG1B of the firstand second other memory cell groups MCH1 and MCH2.

Here, the control gates of the third and fourth drain side selecttransistors SDT3 and SDT4 are connected to the first and second drainside select gates SGD1 and SGD2 of the first and second drain sideselect transistors SDT1 and SDT2, respectively.

Furthermore, the control gates of the third and fourth source sideselect transistors SST3 and SST4 are connected to the first and secondsource side select gates SGS1 and SGS2 of the first and second sourceside select transistors SST1 and SST2, respectively.

The third connecting portion transistor CPT3 is provided between thethird memory cell group MCG3 and the third source side select transistorSST3, includes a channel formed in the third semiconductor layer SEM3,and includes a second connecting portion gate CPG2. In the followingdescription, a second back gate BG2 is illustratively used as the secondconnecting portion gate CPG2.

The fourth connecting portion transistor CPT4 is provided between thefourth memory cell group MCG4 and the fourth source side selecttransistor SST4, includes a channel formed in the fourth semiconductorlayer SEM4, and includes a select gate connected to the secondconnecting portion gate CPG2.

In the case where the nonvolatile semiconductor memory device 102includes the third and fourth memory strings MCS3 and MCS4 thusconfigured, in the selective erase operation ER in a selected celltransistor CL1 of the first memory transistors MC1A (memory cells MCbelonging to the first memory cell group MCG1), the control unit CTUfurther applies the second voltage (0 V) to the second back gate BG2.

Under the above voltage relationship, erroneous writing in the third andfourth memory strings MCS3 and MCS4 is suppressed, and the desiredselected transistor (in this case, the selected cell transistor CL1 ofthe first memory transistors MC1A) can be selectively erased.

(Write Operation WR)

In the following, a description is given of the operation of the controlunit CTU in the write operation WR in this nonvolatile semiconductormemory device 102.

In the write operation WR in the selected cell transistor CL1 of thefirst memory transistors MC1A, the control unit CTU performs thefollowing operation.

The control unit CTU applies the second voltage V2 (0 V) to the firstbit line BL1. Furthermore, the selected cell gate (control gate CG0/1-3)of the selected cell transistor CL1 is subjected to the first voltage V1(high voltage Vpp).

The non-selected cell gates (control gate CG0/1-1, control gate CG0/1-2,and control gate CG0/1-4) of the first memory transistors MC1A otherthan the selected cell transistor CL1 are subjected to the fifth voltageV5 (e.g., low voltage Vcc).

The first drain side select gate SGD1 is subjected to the fifth voltageV5 (low voltage Vcc).

The second bit line BL2 is subjected to the fifth voltage V5 (lowvoltage Vcc).

Furthermore, the control unit CTU applies the fifth voltage V5 (lowvoltage Vcc) or the second voltage V2 (0 V) to the first source line SL1or sets the first source line SL1 in the floating state OPN.

The first other control gate CG1B is subjected to the fifth voltage V5(low voltage Vcc).

The first source side select gate SGS1 is subjected to the secondvoltage V2 (0 V).

The first back gate BG1 is subjected to the fifth voltage V5 (lowvoltage Vcc).

The second source line SL2 is subjected to the second voltage V2 (0 V).

The second control gates CG2A (control gate CG2/3-1 to control gateCG2/3-4) are subjected to the second voltage V2 (0 V) or the fifthvoltage (low voltage Vcc).

The second drain side select gate SGD2 is subjected to the secondvoltage V2 (0 V).

The second source side select gate SGS2 is subjected to the secondvoltage V2 (0 V).

The second back gate BG2 is subjected to the second voltage (0 V).

Thus, the desired select transistor (in this case, the selected celltransistor CL1 belonging to the first memory transistors MC1A) can bewritten.

(Read Operation RD)

Furthermore, a description is given of the operation of the control unitCTU in the read operation RD in this nonvolatile semiconductor memorydevice 102.

In the read operation RD in the selected cell transistor CL1 of thefirst memory transistors MC1A, the control unit CTU performs thefollowing operation.

The control unit CTU applies a reading bit line voltage Ve lower thanthe fifth voltage V5 (e.g., low voltage Vcc) and higher than the secondvoltage V2 (e.g., 0 V) to the first bit line BL1. The reading bit linevoltage Ve can illustratively be 1 V to 2 V.

The selected cell gate (control gate CG0/1-3) of the selected celltransistor CL1 is subjected to the sense voltage Vse.

The non-selected cell gates (control gate CG0/1-1, control gate CG0/1-2,and control gate CG0/1-4) of the first memory transistors MC1A otherthan the selected cell transistor CL1 are subjected to the fifth voltageV5 (low voltage Vcc).

The first drain side select gate SGD1 is subjected to the fifth voltageV5 (low voltage Vcc).

The second bit line BL2 is subjected to the second voltage V2 (0 V).

Furthermore, the control unit CTU applies the second voltage V2 (0 V) tothe first source line SL1.

The first other control gate CG1B is subjected to the fifth voltage V5(low voltage Vcc).

The first source side select gate SGS1 is subjected to the fifth voltageV5 (Vcc).

The first back gate BG1 is subjected to the fifth voltage V5 (lowvoltage Vcc).

The second source line SL2 is subjected to the second voltage V2 (0 V).

The second control gates CG2A (control gate CG2/3-1 to control gateCG2/3-4) are subjected to the second voltage V2 (0 V).

The second drain side select gate SGD2 is subjected to the secondvoltage V2 (0 V).

The second source side select gate SGS2 is subjected to the secondvoltage V2 (0 V).

The second back gate BG2 is subjected to the second voltage (0 V).

Thus, the data stored in the desired select transistor (in this case,the selected cell transistor CL1 belonging to the first memorytransistors MC1A) can be read.

Furthermore, as shown in FIG. 5, also in the case where the selectedmemory cells are the selected cell transistors CL2, CL3, and CL4belonging, respectively, to the second, third, and fourth memory stringsMCS2, MCS3, and MCS4, the voltages under the condition illustrated inFIG. 6 can be used to perform the selective erase operation ER. Morespecifically, the positions of the first memory cell group MCG1, thefirst other memory cell group MCH1, the second memory cell group MCG2,the second other memory cell group MCH2, the third memory cell group,the third other memory cell group, the fourth memory cell group, thefourth other memory cell group and the like can be regarded to changewith the position of the selected memory cell, and the positions of eachwiring, each select gate, each control gate, and each connecting portiongate can be changed accordingly to selectively erase the desired memorycell MC by a similar operation.

Furthermore, the write operation WR and the read operation RD can beperformed likewise.

FIG. 7 is a schematic diagram illustrating the configuration of analternative nonvolatile semiconductor memory device according to thesecond embodiment.

More specifically, FIG. 7 is a circuit diagram illustrating theconfiguration of a nonvolatile semiconductor memory device 102a. In FIG.7, for clarity of illustration, some wirings are not shown.

FIG. 8 is a table illustrating the operation of the alternativenonvolatile semiconductor memory device according to the secondembodiment.

As shown in FIG. 7, in the nonvolatile semiconductor memory device 102a,the first other control gate CG1B and the second other control gate CG2Bare not common and are independent of each other. The rest is same asthe nonvolatile semiconductor memory device 102.

That is, in the nonvolatile semiconductor memory device 102a, each ofthe plurality of second other memory transistors MC2B includes a channelformed in the second semiconductor layer SEM2, includes a second othercontrol gate CG2B, and allows its data to be electrically rewritten.

As shown in FIG. 8, in the nonvolatile semiconductor memory device 102athus configured, in the selective erase operation ER in theaforementioned selected cell transistor CL1 of the aforementioned firstmemory transistors MC1A (memory cells MC belonging to the first memorycell group MCG1), the control unit CTU applies the second voltage (0 V)to the second control gates CG2A (control gate CG2-1 to control gateCG2-4) and the second other control gates CG2B (control gate CG2-5 tocontrol gate CG2-8). The rest is same as the nonvolatile semiconductormemory device 102.

Further, in the write operation WR, the control unit CTU applies thesecond voltage V2 (0 V) or the fifth voltage V5 (lower voltage Vcc) tothe first source line SL1 or sets the first source line in the floatingstate OPN. The second control gate CG2A and the second other controlgate CG2B are subjected to the second voltage V2 (0 V). The rest is sameas the nonvolatile semiconductor memory device 102.

Furthermore, in the read operation RD, the control unit CTU applies thesecond voltage V2 (0 V) to the second control gate CG2A and the secondother control gate CG2B. The rest is same as the nonvolatilesemiconductor memory device 102.

SECOND PRACTICAL EXAMPLE

In the following, a nonvolatile semiconductor memory device 120 of asecond practical example according to the second embodiment isdescribed.

FIGS. 9 and 10 are a schematic perspective view and a schematiccross-sectional view, respectively, illustrating the configuration ofthe nonvolatile semiconductor memory device according to the secondpractical example.

It is noted that for clarity of illustration, FIG. 9 shows only theconductive portions and omits the insulating portions.

As shown in FIGS. 9 and 10, in the nonvolatile semiconductor memorydevice 120 according to this embodiment, two of the semiconductorpillars SP described with reference to the first practical example areconnected by a connecting portion CP.

That is, in addition to the first semiconductor pillar SP1, the memoryunit MU further includes a second semiconductor pillar SP2(semiconductor pillar SP) and a first connecting portion CP1 (connectingportion CP).

The second semiconductor pillar SP2 is adjacent to the firstsemiconductor pillar SP1 (semiconductor pillar SP) illustratively in theY-axis direction and pierces the multilayer structure ML in the Z-axisdirection. The first connecting portion CP1 electrically connects thefirst semiconductor pillar SP1 and the second semiconductor pillar SP2on the same side (substrate 11 side) in the Z-axis direction. The firstconnecting portion CP1 aligns in the Y-axis direction. The firstconnecting portion CP1 is made of the same material as the first andsecond semiconductor pillars SP1 and SP2.

More specifically, a back gate BG (connecting portion conductive layer)is provided on the major surface 11a of the substrate 11 via theinterlayer insulating film 13. A trench is provided in portions of thefirst back gate BG1 (back gate BG) opposed to the first and secondsemiconductor pillars SP1 and SP2. An outer insulating film 43, a memorylayer 48, and an inner insulating film 42 are formed inside the trench,and the remaining space is filled with a connecting portion CP made of asemiconductor. It is noted that the formation of the outer insulatingfilm 43, the memory layer 48, the inner insulating film 42, and theconnecting portion CP in the trench is performed simultaneously andcollectively with the formation of the outer insulating film 43, thememory layer 48, the inner insulating film 42, and the semiconductorpillar SP in the through hole TH. Thus, the back gate BG is providedopposite to the connecting portion CP.

That is, the first connecting portion CP1 and the first back gate BG1constitute the first connecting portion transistor CPT1 illustrated inFIG. 5.

Thus, the first and second semiconductor pillars SP1 and SP2 and theconnecting portion CP constitute a U-shaped semiconductor pillar, whichserves as a U-shaped memory string.

Here, as illustrated in FIG. 10, the electrode film WL between the firstand second semiconductor pillars SP1 and SP2 is divided by an insulatinglayer IL.

As shown in FIGS. 9 and 10, the end of the first semiconductor pillarSP1 opposite to the first connecting portion CP1 is connected to a bitline BL (first bit line BL1), and the end of the second semiconductorpillar SP2 opposite to the first connecting portion CP1 is connected toa source line SL (first source line SL1). Here, the semiconductor pillarSP is connected to the bit line BL by a via VA1 and a via VA2.

In this example, the bit line BL aligns in the Y-axis direction, and thesource line SL aligns in the X-axis direction.

Furthermore, between the multilayer structure ML and the bit line BL, afirst drain side select gate SGD1 is provided opposite to the firstsemiconductor pillar SP1, and a first source side select gate SGS1 isprovided opposite to the second semiconductor pillar SP2.

Furthermore, a third semiconductor pillar SP3, a fourth semiconductorpillar SP4, and a second connecting portion CP2 (connecting portion CP)are provided.

The third semiconductor pillar SP3 is adjacent to the secondsemiconductor pillar SP2 on the opposite side of the secondsemiconductor pillar SP2 from the first semiconductor pillar SP1 in theY-axis direction and pierces the multilayer structure ML in the Z-axisdirection. The fourth semiconductor pillar SP4 is adjacent to the thirdsemiconductor pillar SP3 on the opposite side of the third semiconductorpillar SP3 from the second semiconductor pillar SP2 in the Y-axisdirection and pierces the multilayer structure ML in the Z-axisdirection.

The second connecting portion CP2 electrically connects the thirdsemiconductor pillar SP3 and the fourth semiconductor pillar SP4 on thesame side in the Z-axis direction (on the same side as the firstconnecting portion CP1). The second connecting portion CP2 aligns in theY-axis direction and is opposed to the first back gate BG1.

The memory layer 48 is provided also between each of the electrode filmsWL and the third and fourth semiconductor pillars SP3 and SP4 andbetween the back gate BG and the second connecting portion CP2. Theinner insulating film 42 is provided also between the third and fourthsemiconductor pillars SP3 and SP4 and the memory layer 48 and betweenthe memory layer 48 and the second connecting portion CP2. The outerinsulating film 43 is provided also between each of the electrode filmsWL and the memory layer 48 and between the memory layer 48 and the backgate BG.

The source line SL is connected to the third end portion on the oppositeside of the third semiconductor pillar SP3 from the second connectingportion CP2. The bit line BL is connected to the fourth end portion onthe opposite side of the fourth semiconductor pillar SP4 from the secondconnecting portion CP2.

Furthermore, a second source side select gate SGS2 is provided oppositeto the third semiconductor pillar SP3, and a second drain side selectgate SGD2 is provided opposite to the fourth semiconductor pillar SP4.

The select gates SG (first and second drain side select gates SGD1 andSGD2 and first and second source side select gates SGS1 and SGS2) can bemade of any conductive material, such as polysilicon or amorphoussilicon. In this example, the select gates SG are divided in the Y-axisdirection and shaped like strips aligning along the X-axis direction.

Here, with regard to the plurality of semiconductor pillars provided inthe nonvolatile semiconductor memory device 120, when all or any of thesemiconductor pillars are referred to, the wording “semiconductor pillarSP” is used. On the other hand, when a particular semiconductor pillaris referred to in describing the relationship between the semiconductorpillars, for instance, the wording “n-th semiconductor pillar SPn” (n isany integer of one or more) is used. Likewise, with regard to theconnecting portions, the wording “n-th connecting portion CPn” is used.

The first and second semiconductor pillars SP1 and SP2 and the firstconnecting portion CP1 correspond to the first semiconductor layer SEM1,and the third and fourth semiconductor pillars SP3 and SP4 and thesecond connecting portion CP2 correspond to the second semiconductorlayer SEM2.

Furthermore, fifth to eighth semiconductor pillars SP5 to SP8 and thirdand fourth connecting portions CP3 and CP4 are provided adjacent in theX-axis direction to the first to fourth semiconductor pillars SP1-SP4and the first and second connecting portions CP1 and CP2. The fifth andsixth semiconductor pillars SP5 and SP6 and the third connecting portionCP3 correspond to the third semiconductor layer SEM3, and the seventhand eighth semiconductor pillars SP7 and SP8 and the fourth connectingportion CP4 correspond to the fourth semiconductor layer SEM4.

The third and fourth connecting portions CP3 and CP4 align in the Y-axisdirection and is opposed to the second back gate BG2, which alignsparallel to the first back gate BG1.

As shown in FIG. 10, an interlayer insulating film 15 is provided at thetop (on the side farthest from the substrate 11) of the multilayerstructure ML. Furthermore, an interlayer insulating film 16 is providedon the multilayer structure ML, a select gate SG is provided thereon,and an interlayer insulating film 17 is provided between the selectgates SG. A through hole TH is provided in the select gate SG, a selectgate insulating film SG1 of a select transistor is provided on the innerside surface thereof, and a semiconductor is filled inside it. Thissemiconductor is included in the semiconductor pillar SP.

Furthermore, an interlayer insulating film 18 is provided on theinterlayer insulating film 17. A source line SL and vias 22 (vias VA1and VA2) are provided thereon, and an interlayer insulating film 19 isprovided around the source line SL. Furthermore, an interlayerinsulating film 23 is provided on the source line SL, and a bit line BLis provided thereon. The bit line BL is shaped like a strip along the Yaxis.

The interlayer insulating films 15, 16, 17, 18, 19, and 23 and theselect gate insulating film SG1 can illustratively be made of siliconoxide.

Here, as in the wiring connecting unit MU2 illustrated in FIG. 10, atone end in the X-axis direction, one electrode film WL is connected to aword line 32 by a via plug 31 and electrically connected to, forinstance, a driving circuit provided in the substrate 11. Likewise, atthe other end in the X-axis direction, another electrode film WL isconnected to the word line by the via plug and electrically connected tothe driving circuit. That is, the length in the X-axis direction of eachof the electrode films WL stacked in the Z-axis direction is variedstepwise, so that electrical connection to the driving circuit isimplemented by the one electrode film WL at one end in the X-axisdirection and by the other electrode film WL at the other end in theX-axis direction.

In the nonvolatile semiconductor memory device 120 thus configured, thecontrol unit CTU performs the operation illustrated in FIG. 6. Thus, theselective erase operation ER can be performed, and the operationalreliability of the device can be improved. Further, it is possible torewrite data at high speed by selective erasure. Furthermore, thedesired operation can be performed by the write operation WR and theread operation RD illustrated in FIG. 6.

Third Embodiment

FIG. 11 is a schematic diagram illustrating the configuration of anonvolatile semiconductor memory device according to a third embodiment.

More specifically, FIG. 11 is a circuit diagram illustrating theconfiguration of a nonvolatile semiconductor memory device 103. In FIG.11, for clarity of illustration, some wirings are not shown.

FIG. 12 is a table illustrating the operation of the nonvolatilesemiconductor memory device according to the third embodiment. As shownin FIG. 11, in the nonvolatile semiconductor memory device 103 accordingto this embodiment, the semiconductor layer of the memory stringincludes a base semiconductor layer. Each of the memory strings has afolded structure.

More specifically, the nonvolatile semiconductor memory device 103according to this embodiment includes a memory unit MU and a controlunit CTU.

The memory unit MU includes a first memory string MCS1, a first wiringW11, a first other wiring W12, and a first base wiring SB1. In thefollowing description, illustratively, a first bit line BL1 is used asthe first wiring W11, and a first source line SL1 is used as the firstother wiring W12. The first base wiring SB1 is one of a plurality ofbase wirings SB provided in the device.

The first memory string MCS1 includes a first memory cell group MCG1, afirst other memory cell group MCH1, a first select transistor SGT11, afirst other select transistor SGT12, and a first connecting portiontransistor CPT1. In the following description, illustratively, a firstdrain side select transistor SDT1 is used as the first select transistorSGT11, and a first source side select transistor SST1 is used as thefirst other select transistor SGT12.

The first memory cell group MCG1 includes a plurality of first memorytransistors MC1A connected in series. Each of the plurality of firstmemory transistors MC1A includes a channel formed in a firstsemiconductor layer SEM1 provided in contact with a first basesemiconductor layer BSEM1. Each of the plurality of first memorytransistors MC1A includes a first control gate CG1A and allows its datato be electrically rewritten.

The first drain side select transistor SDT1 is provided on one end sideof the first memory cell group MCG1, includes a channel formed in thefirst semiconductor layer SEM1, and includes a first select gate SG11.In the following description, a first drain side select gate SGD1 isillustratively used as the first select gate SG11.

The first source side select transistor SST1 is provided on the oppositeside of the first memory cell group MCG1 from the first drain sideselect transistor SDT1, includes a channel formed in the firstsemiconductor layer SEM1, and includes a first other select gate SG12.In the following description, a first source side select gate SGS1 isillustratively used as the first other select gate SG12.

The first connecting portion transistor CPT1 is provided between thefirst memory cell group MCG1 and the first source side select transistorSST1, includes a channel formed in the first semiconductor layer SEM1,and includes a first connecting portion gate CPG1. In the followingdescription, a first back gate BG1 is illustratively used as the firstconnecting portion gate CPG1.

The first other memory cell group MCH1 is provided between the firstsource side select transistor SST1 and the first connecting portiontransistor CPT1 and includes a plurality of first other memorytransistors MC1B connected in series.

Each of the plurality of first other memory transistors MC1B includes achannel formed in the first semiconductor layer SEM1, includes a firstother control gate CG1B, and allows its data to be electricallyrewritten.

The first bit line BL1 is connected to the first semiconductor layerSEM1 on the opposite side of the first drain side select transistor SDT1from the first memory cell group MCG1.

The first source line SL1 is connected to the first semiconductor layerSEM1 on the opposite side of the first source side select transistorSST1 from the first other memory cell group MCH1.

The first base wiring SB1 is connected to the first base semiconductorlayer BSEM1.

In the nonvolatile semiconductor memory device 103, the bit line and thesource line are arranged parallel to each other and cross (e.g.,orthogonally) the select gate, the control gate, and the back gate.

(Selective Erase Operation ER)

In the following, a description is given of the operation of the controlunit CTU in the selective erase operation ER in this nonvolatilesemiconductor memory device 103.

In the selective erase operation ER in a selected cell transistor CL1 ofthe first memory transistors MC1A (memory cells MC belonging to thefirst memory cell group MCG1), the control unit CTU performs thefollowing operation. Here, this selected cell transistor CL1 includesthe control gate CG1-3.

As shown in FIG. 12, the control unit CTU applies a first voltage V1(e.g., high voltage Vpp, such as 20 V) to the first bit line BL1 and thefirst source line SL1. Alternatively, the control unit CTU sets thefirst bit line BL1 and the first source line SL1 in the floating stateOPN.

Furthermore, the selected cell gate CG1-3 of the selected celltransistor CL1 is subjected to a second voltage V2 (e.g., 0 V) lowerthan the first voltage V1.

The non-selected cell gates (control gate CG1-1, control gate CG1-2, andcontrol gate CG1-4) of the first memory transistors MC1A other than theselected cell transistor CL1 are subjected to a third voltage V3 (e.g.,medium voltage Vm, such as 10 V) lower than the first voltage V1 andhigher than the second voltage V2.

The first other control gates CG1B (control gate CG1-5 to control gateCG1-8) are subjected to the third voltage V3 (e.g., medium voltage Vm).

The first drain side select gate SGD1 and the first source side selectgate SGS1 are subjected to a tenth voltage V10 lower than the firstvoltage V1 and higher than the second voltage V2. The medium voltage Vm(e.g., 10 V) is illustratively used as the tenth voltage V10.

The first back gate BG1 is subjected to an eleventh voltage V11 lowerthan the first voltage V1 and higher than the second voltage V2. Themedium voltage Vm can be used as the eleventh voltage V11.

The first base wiring SB1 is subjected to the first voltage V1 (e.g.,high voltage Vpp, such as 20 V).

Under this voltage relationship, a high electric field is appliedbetween the charge retention layer of the selected cell transistor CL1and the first base semiconductor layer BSEM1, which results in at leastone of release of electrons from the charge retention layer toward thefirst base semiconductor layer BSEM1 and injection of holes into thecharge retention layer. Thus, the threshold voltage of the selected celltransistor CL1 falls below 0 V.

In the non-selected memory cells belonging to the same memory cell groupas the selected cell transistor CL1, the control gates are subjected tothe medium voltage Vm (e.g., 10 V), and hence the applied electric fieldis low. Thus, the non-selected memory cells are not erased.

In addition, as shown in FIG. 11, the memory unit MU can further includea second memory string MCS2.

The second memory string MCS2 includes a second memory cell group MCG2,a second other memory cell group MCH2, a second select transistor SGT21,a second other select transistor SGT22, and a second connecting portiontransistor CPT2. In the following description, illustratively, a seconddrain side select transistor SDT2 is used as the second selecttransistor SGT21, and a second source side select transistor SST2 isused as the second other select transistor SGT22.

The second memory cell group MCG2 includes a plurality of second memorytransistors MC2A connected in series. Each of the plurality of secondmemory transistors MC2A includes a channel formed in a secondsemiconductor layer SEM2 provided in contact with a second basesemiconductor layer BSEM2 and electrically isolated from the firstsemiconductor layer SEM1, includes a second control gate CG2A, andallows its data to be electrically rewritten.

The second drain side select transistor SDT2 is provided on one end sideof the second memory cell group MCG2, includes a channel formed in thesecond semiconductor layer SEM2, and includes a second select gate SG21.In the following description, a second drain side select gate SGD2 isillustratively used as the second select gate SG21.

The second source side select transistor SST2 is provided on theopposite side of the second memory cell group MCG2 from the second drainside select transistor SDT2, includes a channel formed in the secondsemiconductor layer SEM2, and includes a second other select gate SG22.In the following description, a second source side select gate SGS2 isillustratively used as the second other select gate SG22.

The second connecting portion transistor CPT2 is provided between thesecond memory cell group MCG2 and the second source side selecttransistor SST2, includes a channel formed in the second semiconductorlayer SEM2, and includes a second connecting portion gate CPG2. In thefollowing description, a second back gate BG2 is illustratively used asthe second connecting portion gate CPG2.

The second other memory cell group MCH2 is provided between the secondsource side select transistor SST2 and the second connecting portiontransistor CPT2 and includes a plurality of second other memorytransistors MC2B connected in series.

Each of the plurality of second other memory transistors MC2B includes achannel formed in the second semiconductor layer SEM2, includes a secondother control gate CG2B, and allows its data to be electricallyrewritten.

In the selective erase operation ER in the aforementioned selected celltransistor CL1 of the aforementioned first memory transistors MC1A(memory cells MC belonging to the first memory cell group MCG1), asshown in FIG. 12, the control unit CTU applies the third voltage V3(medium voltage Vm) to the second control gates CG2A (control gate CG2-1to control gate CG2-4) and the second other control gates CG2B (controlgate CG2-5 to control gate CG2-8).

The second drain side select gate SGD2 and the second source side selectgate SGS2 are subjected to the tenth voltage V10.

The second back gate BG2 is subjected to the eleventh voltage V11.

Here, as described above, the first base wiring SB1 is subjected to thefirst voltage V1 (e.g., high voltage Vpp, or 20 V).

Erroneous erasure is suppressed in the memory cells MC belonging to thesecond memory string MCS2 commonly connected to the first base wiringSB1, the first bit line BL1, and the first source line SL1 because thesecond drain side select gate SGD2, the second source side select gateSGS2, the second control gate CG2A and second other control gates CG2B(control gate CG2-1 to control gate CG2-8), and the second back gate BG2are subjected to the medium voltage Vm (10 V).

Thus, the non-selected memory cells of the second memory transistorsMC2A and the second other memory transistors MC2B belonging to thesecond memory string MCS2 are not erased.

In addition, as shown in FIG. 11, the memory unit MU can further includea third memory string MCS3, a second wiring W21, a second other wiringW22, and a second base wiring SB2. In the following description,illustratively, a second bit line BL2 is used as the second wiring W21,and a second source line SL2 is used as the second other wiring W22. Thesecond base wiring SB2 is one of the plurality of base wirings SBprovided in the device.

The third memory string MCS3 includes a third memory cell group MCG3, athird other memory cell group MCH3, a third select transistor SGT31, athird other select transistor SGT32, and a third connecting portiontransistor CPT3. In the following description, illustratively, a thirddrain side select transistor SDT3 is used as the third select transistorSGT31, and a third source side select transistor SST3 is used as thethird other select transistor SGT32.

The third memory cell group MCG3 includes a plurality of third memorytransistors MC3A connected in series. Each of the plurality of thirdmemory transistors MC3A includes a channel formed in a thirdsemiconductor layer SEM3 provided in contact with a third basesemiconductor layer BSEM3 and electrically isolated from the firstsemiconductor layer SEM1 and the second semiconductor layer SEM2, isconnected to the first control gate CG1A, and allows its data to beelectrically rewritten.

The third drain side select transistor SDT3 is provided on one end sideof the third memory cell group MCG3, includes a channel formed in thethird semiconductor layer SEM3, and is connected to the first selectgate SG11.

The third source side select transistor SST3 is provided on the oppositeside of the third memory cell group MCG3 from the third drain sideselect transistor SDT3, includes a channel formed in the thirdsemiconductor layer SEM3, and is connected to the first other selectgate SG12.

The third connecting portion transistor CPT3 is provided between thethird memory cell group MCG3 and the third source side select transistorSST3, includes a channel formed in the third semiconductor layer SEM3,and is connected to the first connecting portion gate CPG1.

The third other memory cell group MCH3 is provided between the thirdsource side select transistor SST3 and the third connecting portiontransistor CPT3 and includes a plurality of third other memorytransistors MC3B connected in series.

Each of the plurality of third other memory transistors MC3B includes achannel formed in the third semiconductor layer SEM3, is connected tothe first other control gate CG1B, and allows its data to beelectrically rewritten.

The second bit line BL2 is connected to the third semiconductor layerSEM3 on the opposite side of the third drain side select transistor SDT3from the third memory cell group MCG3.

The second source line SL2 is connected to the third semiconductor layerSEM3 on the opposite side of the third source side select transistorSST3 from the third other memory cell group MCH3.

The second base wiring SB2 is connected to the third base semiconductorlayer BSEM3.

In the selective erase operation ER in the aforementioned selected celltransistor CL1 of the aforementioned first memory transistors MC1A(memory cells MC belonging to the first memory cell group MCG1), asshown in FIG. 12, the control unit CTU further applies a twelfth voltageV12 lower than the first voltage V1 and higher than the second voltageV2 to the second bit line BL2 and the second source line SL2.Alternatively, the control unit CTU sets the second bit line BL2 and thesecond source line SL2 in the floating state OPN. The medium voltage Vm(e.g., 10 V) can illustratively be used as the twelfth voltage V12.

The second base wiring SB2 is subjected to a thirteenth voltage V13lower than the first voltage V1 and higher than the second voltage V2.The medium voltage Vm (e.g., 10 V) can illustratively be used as thethirteenth voltage V13. Alternatively, the second base wiring SB2 may beset in the floating state OPN.

Thus, in the memory cells MC belonging to the memory string (thirdmemory string MCS3) commonly connected to the control gate CG, selectgate SG, and back gate BG of the memory cell group to which the selectedcell transistor CL1 belongs, the second bit line BL2 and the secondsource line SL2 are subjected to the medium voltage Vm (10 V) or set inthe floating state OPN, and hence no electric field is applied thereto.Thus, these memory cells MC are not erased.

In addition, as shown in FIG. 11, the memory unit MU can further includea fourth memory string MCS4.

The fourth memory string MCS4 includes a fourth memory cell group MCG4,a fourth other memory cell group MCH4, a fourth select transistor SGT41,a fourth other select transistor SGT42, and a fourth connecting portiontransistor CPT4. In the following description, illustratively, a fourthdrain side select transistor SDT4 is used as the fourth selecttransistor SGT41, and a fourth source side select transistor SST4 isused as the fourth other select transistor SGT42.

The fourth memory cell group MCG4 includes a plurality of fourth memorytransistors MC4A connected in series. Each of the plurality of fourthmemory transistors MC4A includes a channel formed in a fourthsemiconductor layer SEM4 provided in contact with a fourth basesemiconductor layer BSEM4 and electrically isolated from the firstsemiconductor layer SEM1, the second semiconductor layer SEM2, and thethird semiconductor layer SEM3, is connected to the second control gateCG2A, and allows its data to be electrically rewritten.

The fourth drain side select transistor SDT4 is provided on one end sideof the fourth memory cell group MCG4, includes a channel formed in thefourth semiconductor layer SEM4, and is connected to the second selectgate SG21.

The fourth source side select transistor SST4 is provided on theopposite side of the fourth memory cell group MCG4 from the fourth drainside select transistor SDT4, includes a channel formed in the fourthsemiconductor layer SEM4, and is connected to the second other selectgate SG22.

The fourth connecting portion transistor CPT4 is provided between thefourth memory cell group MCG4 and the fourth source side selecttransistor SST4, includes a channel formed in the fourth semiconductorlayer SEM4, and is connected to the second connecting portion gate CPG2.

The fourth other memory cell group MCH4 is provided between the fourthsource side select transistor SST4 and the fourth connecting portiontransistor CPT4 and includes a plurality of fourth other memorytransistors MC4B connected in series.

Each of the plurality of fourth other memory transistors MC4B includes achannel formed in the fourth semiconductor layer SEM4, is connected tothe second other control gate CG2B, and allows its data to beelectrically rewritten.

The second bit line BL2 is further connected to the fourth semiconductorlayer SEM4 on the opposite side of the fourth drain side selecttransistor SDT4 from the fourth memory cell group MCG4.

The second source line SL2 is further connected to the fourthsemiconductor layer SEM4 on the opposite side of the fourth source sideselect transistor SST4 from the fourth other memory cell group MCH4.

The second base wiring SB2 is further connected to the fourth basesemiconductor layer BSEM4.

Also in each memory cell MC of the fourth memory string MCS4 thusconfigured, like the second memory string MCS2 and the third memorystring MCS3, no erasure occurs.

(Write Operation)

In the following, a description is given of the operation of the controlunit CTU in the write operation WR in this nonvolatile semiconductormemory device 103.

In the write operation WR in the selected cell transistor CL1 of thefirst memory transistors MC1A, the control unit CTU performs thefollowing operation.

The control unit CTU applies the second voltage V2 (0 V) to the firstbit line BL1. Furthermore, the selected cell gate (control gate CG1-3)of the selected cell transistor CL1 is subjected to the first voltage V1(high voltage Vpp).

The non-selected cell gates (control gate CG1-1, control gate CG1-2, andcontrol gate CG1-4) of the first memory transistors MC1A other than theselected cell transistor CL1 are subjected to the fifth voltage V5 (lowvoltage Vcc).

The first drain side select gate SGD1 is subjected to the fifth voltageV5 (low voltage Vcc).

The second bit line BL2 is subjected to the fifth voltage V5 (lowvoltage Vcc). Alternatively, the second bit line BL2 is set in thefloating state OPN.

The first base wiring SB1 is subjected to the second voltage V2 (0 V).

Furthermore, the control unit CTU applies the second voltage V2 (0 V) orthe fifth voltage V5 (low voltage Vcc) to the first source line SL1 orsets the first source line SL1 in the floating state OPN.

The first other control gates CG1B (control gate CG1-5 to control gateCG1-8) are subjected to the fifth voltage V5 (low voltage Vcc).

The first source side select gate SGS1 is subjected to the secondvoltage V2 (0 V).

The first back gate BG1 is subjected to the fifth voltage V5 (lowvoltage Vcc).

The second source line SL2 is subjected to the second voltage V2 (0 V)or the fifth voltage V5 (low voltage Vcc), or the second source line SL2is set in the floating state OPN.

The second control gates CG2A (control gate CG2-1 to control gate CG2-4)and the second other control gates CG2B (control gate CG2-5 to controlgate CG2-8) are subjected to the second voltage V2 (0 V) or the lowvoltage Vcc. The second drain side select gate SGD2 and the second backgate BG2 are subjected to the second voltage V2 (0 V) or the low voltageVcc, or the second drain side select gate SGD2 and the second back gateBG2 are set in the floating state OPN. Here, the second control gateCG2A and the second other control gate CG2B, and the second drain sideselect gate SGD2 and the second back gate BG2 may be subjected to 0 Valso in the case where the second voltage V2 is not 0 V.

The second source side select gate SGS2 is subjected to the secondvoltage V2 (0 V) or the fifth voltage (low voltage Vcc), or the secondsource side select gate SGS2 is set in the floating state OPN.

Furthermore, the second base wiring SB2 is subjected to the low voltageVcc. Alternatively, the second base wiring SB2 is set in the floatingstate OPN. Here, in the case where the second voltage V2 is not 0 V, thesecond base wiring SB2 may be subjected to 0 V.

Thus, the desired select transistor (in this case, the selected celltransistor CL1 belonging to the first memory transistors MC1A) can bewritten.

More specifically, a high electric field is applied between the chargeretention layer of the selected cell transistor CL1 and the first basesemiconductor layer BSEM1. Hence, electrons are injected into the chargeretention layer, or holes are released into the first base semiconductorlayer BSEM1. Thus, the threshold voltage of the selected cell transistorCL1 exceeds 0V.

In the non-selected memory cells belonging to the same memory cell groupas the selected cell transistor CL1, the applied electric field is low,and hence no writing occurs.

On the other hand, writing is prevented in the memory cells MC includedin the memory string adjacent to the memory string commonly connected tothe first control gate CG1A and the first other control gates CG1B(control gate CG1-1 to control gate CG1-8), the first drain side selectgate SGD1, the first source side select gate SGS1, and the first backgate BG1 and including the selected cell transistor CL because thesecond bit line BL2 is subjected to the low voltage Vcc (e.g., 3 V) orset in the floating state OPN and the second source line SL2 issubjected to the second voltage V2 (0 V) or the fifth voltage (lowvoltage Vcc), or the second source side select gate SGS2 is set in thefloating state OPN.

Furthermore, erroneous writing is prevented in the memory stringcommonly connected to the first base wiring SB1, the first bit line BL1,and the first source line SL1 because the second drain side select gateSGD2 and the second source side select gate SGS2, the second controlgate CG2A and the second other control gates CG2B (control gate CG2-1 tocontrol gate CG2-8), and the second back gate BG2 are subjected to thelow voltage Vcc (e.g., 3 V) or 0 V.

(Read Operation RD)

Furthermore, a description is given of the operation of the control unitCTU in the read operation RD in this nonvolatile semiconductor memorydevice 103.

In the read operation RD in the selected cell transistor CL1 of thefirst memory transistors MC1A, the control unit CTU performs thefollowing operation.

The control unit CTU applies a reading bit line voltage Ve not higherthan the fifth voltage V5 (e.g., low voltage Vcc) and higher than thesecond voltage V2 (e.g., 0 V) to the first bit line BL1. The reading bitline voltage Ve can illustratively be 1 V to 2 V.

The selected cell gate (control gate CG1-3) of the selected celltransistor CL1 is subjected to the sense voltage Vse.

The non-selected cell gates (control gate CG1-1, control gate CG1-2, andcontrol gate CG1-4) of the first memory transistors MC1A other than theselected cell transistor CL1 are subjected to the fifth voltage V5 (lowvoltage Vcc).

The first drain side select gate SGD1 is subjected to the fifth voltageV5 (low voltage Vcc).

The second bit line BL2 is subjected to the second voltage V2 (0 V).

The first base wiring SB1 is subjected to the second voltage V2 (0 V).

Furthermore, the control unit CTU applies the second voltage V2 (0 V) tothe first source line SL1.

The first other control gates CG1B (control gate CG1-5 to control gateCG1-8) are subjected to the fifth voltage V5 (low voltage Vcc).

The first source side select gate SGS1 is subjected to the fifth voltageV5 (low voltage Vcc).

The first back gate BG1 is subjected to the fifth voltage V5 (lowvoltage Vcc).

The second source line SL2 is subjected to the second voltage V2 (0 V).

The second control gates CG2A (control gate CG2-1 to control gate CG2-4)and the second other control gates CG2B (control gate CG2-5 to controlgate CG2-8) are subjected to the second voltage V2 (0 V).

The second drain side select gate SGD2 is subjected to the secondvoltage V2 (0 V).

The second source side select gate SGS2 is subjected to the secondvoltage V2 (0 V).

The second back gate BG2 is subjected to the second voltage V2 (0 V).

The second base wiring SB2 is subjected to the second voltage V2 (0 V).

Thus, the data stored in the desired select transistor (in this case,the selected cell transistor CL1 belonging to the first memorytransistors MC1A) can be read.

Furthermore, as shown in FIG. 11, also in the case where the selectedmemory cells are the selected cell transistors CL2, CL3, and CL4belonging, respectively, to the second, third, and fourth memory string,MCS2, MCS3, and MCS4, the voltages under the condition illustrated inFIG. 12 can be used to perform the selective erase operation ER.

Furthermore, the write operation WR and the read operation RD can beperformed likewise.

In the nonvolatile semiconductor memory device 103 according to thisembodiment, the base semiconductor layer is not isolated for each memorycell group, but is shared by the adjacent memory cell groups like eachbit line BL and each source line SL. In the structure in which the basesemiconductor layer is isolated for each memory cell group, selectiveerasure can be performed by applying the second voltage V2 (0 V) to theselect gate SG, control gate CG, and back gate BG of the memory cellgroups sharing the bit line BL and the source line SL. This has theadvantage of reducing the number of terminals to be energized.

FIG. 13 is a schematic diagram illustrating the configuration of analternative nonvolatile semiconductor memory device according to thethird embodiment.

More specifically, FIG. 13 is a circuit diagram illustrating theconfiguration of a nonvolatile semiconductor memory device 103a. In FIG.13, for clarity of illustration, some wirings are not shown.

FIG. 14 is a table illustrating the operation of the alternativenonvolatile semiconductor memory device according to the thirdembodiment.

As shown in FIG. 13, in the nonvolatile semiconductor memory device103a, the first other control gate CG1B of the first other memorytransistor MC1B is electrically connected to the control gate of thesecond other memory transistor MC2B. The rest is same as the nonvolatilesemiconductor memory device 103.

That is, in the nonvolatile semiconductor memory device 103a, each ofthe plurality of second other memory transistors MC2B includes a channelformed in the second semiconductor layer SEM2, includes the control gate(second other control gate) electrically connected to the first othercontrol gate CG1B, and allows its data to be electrically rewritten.

As shown in FIG. 14, in the nonvolatile semiconductor memory device 103athus configured, in the selective erase operation ER, the writeoperation WR, and the read operation RD, the control unit CTU implementsthe same operations as the nonvolatile semiconductor memory device 103.

THIRD PRACTICAL EXAMPLE

In the following, a nonvolatile semiconductor memory device 130 of athird practical example according to the third embodiment is described.

FIG. 15 is a schematic perspective view illustrating the configurationof the nonvolatile semiconductor memory device according to the thirdpractical example.

More specifically, FIG. 15 illustrates the configuration of the firstand third memory strings MCS1 and MCS3.

As shown in FIG. 15, in the nonvolatile semiconductor memory device 130,an interlayer insulating film 13 is provided on a substrate, not shown,and a multilayer structure ML with electrode films WL and interelectrodeinsulating films 14 alternately stacked therein is provided on theinterlayer insulating film 13. Furthermore, a select gate SG is providedthereon, and an interlayer insulating film 18 is provided thereon.

Furthermore, a trench TR is formed in the interlayer insulating film 18,the select gate SG, and the multilayer structure ML. A back gate (firstback gate BG1) is provided at the bottom of the trench TR. A stackedinsulating film 49 of an outer insulating film 43, a memory layer 48,and an inner insulating film 42 is provided on the inner wall of thetrench and on the back gate BG. The remaining space inside it is filledwith a semiconductor layer SEML illustratively made of p-typepolysilicon. The portion of this semiconductor layer SEML near theelectrode film WL serves as a first semiconductor layer SEM1.Furthermore, the central portion of the semiconductor layer SEML awayfrom the electrode film WL serves as a base semiconductor layer (firstbase semiconductor layer BSEM1). A p⁺-region P01, for instance, having ahigher impurity concentration than the first base semiconductor layerBSEM1 is provided in an upper portion of the first base semiconductorlayer BSEM1 and serves as a contact portion of the first base wiring SB1in the first base semiconductor layer BSEM1.

A first drain side select transistor SDT1 is provided on one wallsurface side of the trench TR, and a first source side select transistorSST1 is provided on the other wall surface side of the trench TR. Thatis, the select gate SG on one wall surface side of the trench TR servesas a first drain side select gate SGD1, and the select gate SG on theother wall surface side of the trench TR serves as a first source sideselect gate SGS1. Here, the stacking direction of the multilayerstructure ML is the Z-axis direction, and the direction in which thewall surfaces of the trench TR are opposed to each other is the Y-axisdirection. Also in this case, the direction perpendicular to the Z-axisdirection and the Y-axis direction is the X-axis direction.

An n⁺-region P02 illustratively having a higher impurity concentrationthan the first base semiconductor layer BSEM1 is provided in an upperportion of the first semiconductor layer SEM1. The n⁺-region P02 on onewall surface side of the trench TR constitutes a drain side contactDC01, and the n⁺-region P02 on the other wall surface side of the trenchTR constitutes a source side contact SC01.

A third memory string MCS3 having the same configuration as the firstmemory string MCS1 is provided adjacent to the first memory string MCS1in the X-axis direction.

In the nonvolatile semiconductor memory device 130 thus configured, thecontrol unit CTU performs the operation illustrated in FIG. 12. Thus,the selective erase operation ER can be performed, and the operationalreliability of the device can be improved. Further, it is possible torewrite data at high speed by selective erasure. Furthermore, thedesired operation can be performed by the write operation WR and theread operation RD illustrated in FIG. 12.

The nonvolatile semiconductor memory devices 101 to 103, 110, 120, and130 according to the above first to third embodiments and the first tothird practical examples enable selective erasure. This improvesreliability because no stress due to unnecessary data rewrite is appliedto the memory cell. Furthermore, the data rewrite speed is increasedbecause data rewrite is needed only in the memory cell requiring datarewrite in the high-capacity memory cell array.

In the nonvolatile semiconductor memory devices according to theembodiments and practical examples of the invention, the interelectrodeinsulating film 14, the inner insulating film 42, and the outerinsulating film 43 can be a monolayer film made of a material selectedfrom a group including silicon oxide, silicon nitride, siliconoxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafniumaluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate,hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate, or amultilayer film made of a plurality of materials selected from thegroup.

The memory layer 48 can be a monolayer film made of a material selectedfrom a group including silicon nitride, silicon oxynitride, aluminumoxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride,hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate,lanthanum oxide, and lanthanum aluminate, or a multilayer film made of aplurality of materials selected from the group.

In the specification of the application, “perpendicular”and “parallel”refer to not only strictly perpendicular and strictly parallel but alsoinclude, for instance, the fluctuation due to manufacturing processes,etc. It is sufficient to be substantially perpendicular andsubstantially parallel.

The embodiments of the invention have been described with reference toexamples. However, the invention is not limited to these examples. Forinstance, various specific configurations of the components, such as thememory unit, control unit, semiconductor substrate, electrode film,insulating film, insulating layer, multilayer structure, memory layer,charge storage layer, semiconductor pillar, semiconductor layer, basesemiconductor layer, word line, bit line, source line, wiring, memorytransistor, and select transistor constituting the nonvolatilesemiconductor memory device are encompassed within the scope of theinvention as long as those skilled in the art can similarly practice theinvention and achieve similar effects by suitably selecting suchconfigurations from conventionally known ones.

Furthermore, any two or more components of the examples can be combinedwith each other as long as technically feasible, and such combinationsare also encompassed within the scope of the invention as long as theyfall within the spirit of the invention.

Furthermore, those skilled in the art can suitably modify and implementthe nonvolatile semiconductor memory device described above in theembodiments of the invention, and all the nonvolatile semiconductormemory devices thus modified are also encompassed within the scope ofthe invention as long as they fall within the spirit of the invention.

Furthermore, those skilled in the art can conceive various modificationsand variations within the spirit of the invention, and it is understoodthat such modifications and variations are also encompassed within thescope of the invention. For instance, those skilled in the art cansuitably modify the above embodiments by addition, deletion, or designchange of components, or by addition, omission, or condition change ofprocesses, and such modifications are also encompassed within the scopeof the invention as long as they fall within the spirit of theinvention.

The invention claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a memory unit; and a control unit, the memory unit includinga first memory string, a first wiring, a second memory string, and asecond wiring, the first memory string including a first memory cellgroup and a first select transistor, the first memory cell groupincluding a plurality of first memory transistors connected in series,each of the plurality of first memory transistors including a channelformed in a first semiconductor layer, including a first control gate,and allowing data of the each of the plurality of first memorytransistors to be electrically rewritten, the first select transistorbeing provided on one end side of the first memory cell group, includinga channel formed in the first semiconductor layer, and including a firstselect gate, the first wiring being connected to the first semiconductorlayer on a side of the first select transistor opposite to the firstmemory cell group, the second memory string including a second memorycell group and a second select transistor, the second memory cell groupincluding a plurality of second memory transistors connected in series,each of the plurality of second memory transistors including a channelformed in a second semiconductor layer electrically isolated from thefirst semiconductor layer, including a control gate electricallyconnected to the first control gate, and allowing data of the each ofthe plurality of second memory transistors to be electrically rewritten,the second select transistor being provided on one end side of thesecond memory cell group, including a channel formed in the secondsemiconductor layer, and including a select gate connected to the firstselect gate, the second wiring being connected to the secondsemiconductor layer on a side of the second select transistor oppositeto the second memory cell group, in a selective erase operation forperforming at least one of injection of a hole into a charge retentionlayer of a selected cell transistor in the selective erase operation ofthe first memory transistors and extraction of an electron from thecharge retention layer of the selected cell transistor in the selectiveerase operation, the control unit being configured to: apply a firstvoltage to the first wiring, apply a second voltage lower than the firstvoltage to a selected cell gate of the first control gate of theselected cell transistor in the selective erase operation, apply a thirdvoltage not higher than the first voltage and higher than the secondvoltage to a non-selected cell gate in the selective erase operation ofthe first control gate of the first memory transistors other than theselected cell transistor in the selective erase operation, apply thefirst voltage or a fourth voltage not higher than the first voltage andnot lower than the third voltage to the first select gate, and apply thesecond voltage or a fifth voltage higher than the second voltage and nothigher than the third voltage to the second wiring or set the secondwiring in a floating state.
 2. The device according to claim 1, whereinthe second voltage is 0 volts, and the third voltage is substantiallyequal to the fourth voltage.
 3. The device according to claim 1, furthercomprising: a substrate, the first semiconductor layer and the secondsemiconductor layer aligning in a direction perpendicular to a majorsurface of the substrate.
 4. The device according to claim 1, wherein ina selective write operation for performing at least one of injection ofan electron into a charge retention layer of a selected cell transistorin the selective write operation of the first memory transistors andextraction of a hole from the charge retention layer of the selectedcell transistor in the selective write operation, the control unit isconfigured to: apply the first voltage to a selected cell gate of thefirst control gate of the selected cell transistor in the selectivewrite operation, apply the second voltage to the first wiring, apply avoltage higher than the second voltage and not higher than the thirdvoltage to a non-selected cell gate in the selective write operation ofthe first control gate of the first memory transistors other than theselected cell transistor in the selective write operation, apply avoltage higher than the second voltage and not higher than the thirdvoltage to the first select gate, and apply a voltage higher than thesecond voltage and not higher than the third voltage to the secondwiring.
 5. The device according to claim 1, wherein in a read operationfor reading data written in a selected cell transistor in the readoperation of the first memory transistors, the control unit isconfigured to: apply a reading bit line voltage not higher than thefifth voltage and higher than the second voltage to the first wiring,apply a sense voltage varied between the fifth voltage and the secondvoltage to a selected cell gate of the first control gate of theselected cell transistor in the read operation, apply the fifth voltageto a non-selected cell gate in the read operation of the first controlgate of the first memory transistors other than the selected celltransistor in the read operation, apply the fifth voltage to the firstselect gate, and apply the second voltage to the second wiring.
 6. Thedevice according to claim 1, wherein the memory unit further includes athird memory string, the third memory string includes a third memorycell group and a third select transistor, the third memory cell groupincludes a plurality of third memory transistors connected in series,each of the plurality of third memory transistors includes a channelformed in a third semiconductor layer electrically isolated from thefirst semiconductor layer and the second semiconductor layer, includes asecond control gate, and allows data of the each of the plurality ofthird memory transistors to be electrically rewritten, the third selecttransistor is provided on one end side of the third memory cell group,includes a channel formed in the third semiconductor layer, and includesa second select gate, the first wiring is connected to the thirdsemiconductor layer on a side of the third select transistor opposite tothe third memory cell group, and in the selective erase operation, thecontrol unit is configured to: apply a sixth voltage lower than thethird voltage to the second control gate of the third memorytransistors, and apply a seventh voltage lower than the third voltage tothe second select gate.
 7. The device according to claim 6, wherein thesixth voltage and the seventh voltage are 0 volts.
 8. The deviceaccording to claim 6, wherein in a selective write operation forperforming at least one of injection of an electron into a chargeretention layer of a selected cell transistor in the selective writeoperation of the first memory transistors and extraction of a hole fromthe charge retention layer of the selected cell transistor in theselective write operation, the control unit is configured to: apply avoltage lower than the third voltage to the second control gate of thethird memory transistors, and apply a voltage lower than the thirdvoltage to the second select gate.
 9. The device according to claim 6,wherein in a read operation for reading data written in a selected celltransistor in the read operation of the first memory transistors, thecontrol unit is configured to: apply the second voltage to the secondcontrol gate of the third memory transistors, and apply the secondvoltage to the second select gate.
 10. The device according to claim 1,wherein the memory unit further includes a first other wiring and asecond other wiring, the first memory string further includes a firstother memory cell group, a first other select transistor, and a firstconnecting portion transistor, the first other select transistor isprovided on a side of the first memory cell group opposite to the firstselect transistor, includes a channel formed in the first semiconductorlayer, and includes a first other select gate, the first connectingportion transistor is provided between the first memory cell group andthe first other select transistor, includes a channel formed in thefirst semiconductor layer, and includes a first connecting portion gate,the first other memory cell group is provided between the first otherselect transistor and the first connecting portion transistor andincludes a plurality of first other memory transistors connected inseries, each of the plurality of first other memory transistors includesa channel formed in the first semiconductor layer, includes a firstother control gate, and allows data of the each of the plurality offirst other memory transistors to be electrically rewritten, the firstother wiring is connected to the first semiconductor layer on a side ofthe first other select transistor opposite to the first other memorycell group, the second memory string further includes a second othermemory cell group, a second other select transistor, and a secondconnecting portion transistor, the second other select transistor isprovided on a side of the second memory cell group opposite to thesecond select transistor, includes a channel formed in the secondsemiconductor layer, and includes a second other select gate, the secondconnecting portion transistor is provided between the second memory cellgroup and the second other select transistor, includes a channel formedin the second semiconductor layer, and includes a connecting portiongate electrically connected to the first connecting portion gate, thesecond other memory cell group is provided between the second otherselect transistor and the second connecting portion transistor andincludes a plurality of second other memory transistors connected inseries, each of the plurality of second other memory transistorsincludes a channel formed in the second semiconductor layer, includes asecond other control gate electrically connected to the first othercontrol gate, and allows data of the each of the plurality of secondother memory transistors to be electrically rewritten, the second otherwiring is connected to the second semiconductor layer on a side of thesecond other select transistor opposite to the second other memory cellgroup, and in the selective erase operation, the control unit is furtherconfigured to: apply the fifth voltage or the second voltage to thefirst other wiring or set the first other wiring in a floating state,apply the third voltage to the first other control gate, apply an eighthvoltage lower than the third voltage to the first other select gate,apply a ninth voltage lower than the first voltage and higher than thesecond voltage to the first connecting portion gate, apply the fifthvoltage, the first voltage, or the second voltage to the second otherwiring or set the second other wiring in a floating state, apply thesixth voltage or the third voltage to the second control gate, apply theeighth voltage to the second select gate, and apply the eighth voltageto the second other select gate.
 11. The device according to claim 10,wherein the eighth voltage is substantially equal to the second voltage,and the ninth voltage is substantially equal to the third voltage. 12.The device according to claim 10, further comprising: a substrate, thefirst semiconductor layer and the second semiconductor layer aligning ina direction perpendicular to a major surface of the substrate.
 13. Thedevice according to claim 10, wherein in a selective write operation forperforming at least one of injection of an electron into a chargeretention layer of a selected cell transistor in the selective writeoperation of the first memory transistors and extraction of a hole fromthe charge retention layer of the selected cell transistor in theselective write operation, the control unit is configured to: apply thesecond voltage to the first wiring, apply the first voltage to aselected cell gate of the first control gate of the selected celltransistor in the selective write operation, apply the fifth voltage toa non-selected cell gate in the selective write operation of the firstcontrol gate of the first memory transistors other than the selectedcell transistor in the selective write operation, apply the fifthvoltage to the first select gate, the second wiring, the first othercontrol gate, and the first connecting portion gate, apply the fifthvoltage or the second voltage to the first other wiring or set the firstother wiring in a floating state, apply the second voltage to the firstother select gate, the second other wiring, the second select gate, thesecond other select gate, and the second connecting portion gate, andapply the second voltage or the fifth voltage to the second controlgate.
 14. The device according to claim 10, wherein in a read operationfor reading data written in a selected cell transistor in the readoperation of the first memory transistors, the control unit isconfigured to: apply a reading bit line voltage not higher than thefifth voltage and higher than the second voltage to the first wiring,apply a sense voltage varied between the fifth voltage and the secondvoltage to a selected cell gate of the first control gate of theselected cell transistor in the read operation, apply the fifth voltageto a non-selected cell gate in the read operation of the first controlgate of the first memory transistors other than the selected celltransistor in the read operation, apply the fifth voltage to the firstselect gate, the first other control gate, the first other select gate,and the first connecting portion gate, and apply the second voltage tothe second wiring, the first other wiring, the second other wiring, thesecond control gate, the second select gate, the second other selectgate, and the second connecting portion gate.
 15. A nonvolatilesemiconductor memory device comprising: a memory unit; and a controlunit, the memory unit including a first memory string, a first wiring, afirst other wiring, and a first base wiring, the first memory stringincluding a first memory cell group, a first other memory cell group, afirst select transistor, a first other select transistor, and a firstconnecting portion transistor, the first memory cell group including aplurality of first memory transistors connected in series, each of theplurality of first memory transistors including a channel formed in afirst semiconductor layer provided in contact with a first basesemiconductor layer, including a first control gate, and allowing dataof the each of the plurality of first memory transistors to beelectrically rewritten, the first select transistor being provided onone end side of the first memory cell group, including a channel formedin the first semiconductor layer, and including a first select gate, thefirst other select transistor being provided on a side of the firstmemory cell group opposite to the first select transistor, including achannel formed in the first semiconductor layer, and including a firstother select gate, the first connecting portion transistor beingprovided between the first memory cell group and the first other selecttransistor, including a channel formed in the first semiconductor layer,and including a first connecting portion gate, the first other memorycell group being provided between the first other select transistor andthe first connecting portion transistor and including a plurality offirst other memory transistors connected in series, each of theplurality of first other memory transistors including a channel formedin the first semiconductor layer, including a first other control gate,and allowing data of the each of the plurality of first other memorytransistors to be electrically rewritten, the first wiring beingconnected to the first semiconductor layer on a side of the first selecttransistor opposite to the first memory cell group, the first otherwiring being connected to the first semiconductor layer on a side of thefirst other select transistor opposite to the first other memory cellgroup, the first base wiring being connected to the first basesemiconductor layer, in a selective erase operation for performing atleast one of injection of a hole into a charge retention layer of aselected cell transistor in the selective erase operation of the firstmemory transistors and extraction of an electron from the chargeretention layer of the selected cell transistor in the selective eraseoperation, the control unit being configured to: apply a first voltageto the first wiring and the first other wiring or set the first wiringand the first other wiring in a floating state, apply a second voltagelower than the first voltage to a selected cell gate of the firstcontrol gate of the selected cell transistor in the selective eraseoperation, apply a third voltage lower than the first voltage and higherthan the second voltage to a non-selected cell gate in the selectiveerase operation of the first control gate of the first memorytransistors other than the selected cell transistor in the selectiveerase operation, apply the third voltage to the first other controlgate, apply a tenth voltage lower than the first voltage and higher thanthe second voltage to the first select gate and the first other selectgate, apply an eleventh voltage lower than the first voltage and higherthan the second voltage to the first connecting portion gate, and applythe first voltage to the first base wiring.
 16. The device according toclaim 15, wherein the second voltage is 0 volts, and the tenth voltageand the eleventh voltage are substantially equal to the third voltage.17. The device according to claim 15, wherein the memory unit furtherincludes a second memory string, the second memory string includes asecond memory cell group, a second other memory cell group, a secondselect transistor, a second other select transistor, and a secondconnecting portion transistor, the second memory cell group includes aplurality of second memory transistors connected in series, each of theplurality of second memory transistors includes a channel formed in asecond semiconductor layer provided in contact with a second basesemiconductor layer and electrically isolated from the firstsemiconductor layer, includes a second control gate, and allows data ofthe each of the plurality of second memory transistors to beelectrically rewritten, the second select transistor is provided on oneend side of the second memory cell group, includes a channel formed inthe second semiconductor layer, and includes a second select gate, thesecond other select transistor is provided on a side of the secondmemory cell group opposite to the second select transistor, includes achannel formed in the second semiconductor layer, and includes a secondother select gate, the second connecting portion transistor is providedbetween the second memory cell group and the second other selecttransistor, includes a channel formed in the second semiconductor layer,and includes a second connecting portion gate, the second other memorycell group is provided between the second other select transistor andthe second connecting portion transistor and includes a plurality ofsecond other memory transistors connected in series, each of theplurality of second other memory transistors includes a channel formedin the second semiconductor layer, includes a second other control gate,and allows data of the each of the plurality of second other memorytransistors to be electrically rewritten, the first wiring is furtherconnected to the second semiconductor layer on a side of the secondselect transistor opposite to the second memory cell group, the firstother wiring is further connected to the second semiconductor layer on aside of the second other select transistor opposite to the second othermemory cell group, the first base wiring is further connected to thesecond base semiconductor layer, and in the selective erase operation,the control unit is further configured to: apply the third voltage tothe second control gate and the second other control gate, apply thetenth voltage to the second select gate and the second other selectgate, and apply the eleventh voltage to the second connecting portiongate.
 18. The device according to claim 17, wherein the memory unitfurther includes a third memory string, a second wiring, a second otherwiring, and a second base wiring, the third memory string includes athird memory cell group, a third other memory cell group, a third selecttransistor, a third other select transistor, and a third connectingportion transistor, the third memory cell group includes a plurality ofthird memory transistors connected in series, each of the plurality ofthird memory transistors includes a channel formed in a thirdsemiconductor layer provided in contact with a third base semiconductorlayer and electrically isolated from the first semiconductor layer andthe second semiconductor layer, is connected to the first control gate,and allows data of the each of the plurality of third memory transistorsto be electrically rewritten, the third select transistor is provided onone end side of the third memory cell group, includes a channel formedin the third semiconductor layer, and is connected to the first selectgate, the third other select transistor is provided on a side of thethird memory cell group opposite to the third select transistor,includes a channel formed in the third semiconductor layer, and isconnected to the first other select gate, the third connecting portiontransistor is provided between the third memory cell group and the thirdother select transistor, includes a channel formed in the thirdsemiconductor layer, and is connected to the first connecting portiongate, the third other memory cell group is provided between the thirdother select transistor and the third connecting portion transistor andincludes a plurality of third other memory transistors connected inseries, each of the plurality of third other memory transistors includesa channel formed in the third semiconductor layer, is connected to thefirst other control gate, and allows data of each of the plurality ofthird other memory transistors to be electrically rewritten, the secondwiring is connected to the third semiconductor layer on a side of thethird select transistor opposite to the third memory cell group, thesecond other wiring is connected to the third semiconductor layer on aside of the third other select transistor opposite to the third othermemory cell group, the second base wiring is connected to the third basesemiconductor layer, and in the selective erase operation, the controlunit is further configured to: apply a twelfth voltage lower than thefirst voltage and higher than the second voltage to the second wiringand the second other wiring or set the second wiring and the secondother wiring in the floating state, and apply a thirteenth voltage lowerthan the first voltage and higher than the second voltage to the secondbase wiring or set the second base wiring in the floating state.
 19. Thedevice according to claim 18, wherein in a selective write operation forperforming at least one of injection of an electron into a chargeretention layer of a selected cell transistor in the selective writeoperation of the first memory transistors and extraction of a hole fromthe charge retention layer of the selected cell transistor in theselective write operation, the control unit is configured to: apply thesecond voltage to the first wiring, the first other select gate, and thefirst base wiring, apply a fifth voltage higher than the second voltageand not higher than the third voltage to the first select gate and thefirst connecting portion gate, apply the first voltage to a selectedcell gate of the first control gate of the selected cell transistor inthe selective write operation, apply the fifth voltage to a non-selectedcell gate in the selective write operation of the first control gate ofthe first memory transistors other than the selected cell transistor inthe selective write operation, apply the second voltage or the fifthvoltage to the first other wiring, the second other wiring, the secondselect gate, the second other select gate, the second base wiring, andthe second connecting portion gate or set the first other wiring, thesecond other wiring, the second select gate, the second other selectgate, the second base wiring, and the second connecting portion gate inthe floating state, apply the fifth voltage to the second wiring or setthe second wiring in the floating state, and apply the second voltage orthe fifth voltage to the second control gate and the second othercontrol gate.
 20. The device according to claim 18, wherein in a readoperation for reading data written in a selected cell transistor of thefirst memory transistors, the control unit is configured to: apply areading bit line voltage not higher than a fifth voltage and higher thanthe second voltage to the first wiring, the fifth voltage being higherthan the second voltage and not higher than the third voltage, apply asense voltage varied between the fifth voltage and the second voltage toa selected cell gate of the first control gate of the selected celltransistor in the read operation, apply the fifth voltage to anon-selected cell gate in the read operation of the first control gateof the first memory transistors other than the selected cell transistorin the read operation, apply the fifth voltage to the first select gate,the first other control gate, the first other select gate, and the firstconnecting portion gate, and apply the second voltage to the secondwiring, the first base wiring, the first other wiring, the second otherwiring, the second control gate, the second other control gate, thesecond select gate, the second other select gate, the second connectingportion gate, and the second base wiring.
 21. A nonvolatilesemiconductor memory device comprising: a memory unit; and a controlunit, the memory unit including a first memory string, a first wiring, asecond memory string, a second wiring, a third memory string, a firstother wiring, and a second other wiring, the first memory stringincluding a first memory cell group, a first select transistor, a firstother memory cell group, a first other select transistor, and a firstconnecting portion transistor, the first memory cell group including aplurality of first memory transistors connected in series, each of theplurality of first memory transistors including a channel formed in afirst semiconductor layer, including a first control gate, and allowingdata to be electrically rewritten, the first select transistor beingprovided on one end side of the first memory cell group, including achannel formed in the first semiconductor layer, and including a firstselect gate, the first other select transistor being provided on a sideof the first memory cell group opposite to the first select transistor,including a channel formed in the first semiconductor layer, andincluding a first other select gate, the first connecting portiontransistor being provided between the first memory cell group and thefirst other select transistor, including a channel formed in the firstsemiconductor layer, and including a first connecting portion gate, thefirst other memory cell group being provided between the first otherselect transistor and the first connecting portion transistor, andincluding a plurality of first other memory transistors connected inseries, each of the plurality of first other memory transistorsincluding a channel formed in the first semiconductor layer, including afirst other control gate, and allowing data to be electricallyrewritten, the second memory string including a second memory cellgroup, a second select transistor, a second other memory cell group, asecond other select transistor, and a second connecting portiontransistor, the second memory cell group including a plurality of secondmemory transistors connected in series, each of the plurality of secondmemory transistors including a channel formed in a second semiconductorlayer electrically isolated from the first semiconductor layer,including a second control gate, and allowing data to be electricallyrewritten, the second select transistor being provided on one end sideof the second memory cell group, including a channel formed in thesecond semiconductor layer, and including a second select gate, thesecond other select transistor being provided on a side of the secondmemory cell group opposite to the second select transistor, including achannel formed in the second semiconductor layer, and including a secondother select gate, the second connecting portion transistor beingprovided between the second memory cell group and the second otherselect transistor, including a channel formed in the secondsemiconductor layer, and including a connecting portion gateelectrically connected to the first connecting portion gate, the secondother memory cell group being provided between the second other selecttransistor and the second connecting portion transistor, and including aplurality of second other memory transistors connected in series, eachof the plurality of second other memory transistors including a channelformed in the second semiconductor layer, including a control gateelectrically connected to the first other control gate, and allowingdata to be electrically rewritten, the third memory string including athird memory cell group, a third select transistor, a third other memorycell group, a third other select transistor, and a third connectingportion transistor, the third memory cell group including a plurality ofthird memory transistors connected in series, each of the plurality ofthird memory transistors including a channel formed in a thirdsemiconductor layer electrically isolated from the first semiconductorlayer and the second semiconductor layer, including a control gateelectrically connected to the first control gate, and allowing data tobe electrically rewritten, the third select transistor being provided onone end side of the third memory cell group, including a channel formedin the third semiconductor layer, and including a select gate connectedto the first select gate, the third other select transistor beingprovided on a side of the third memory cell group opposite to the thirdselect transistor, including a channel formed in the third semiconductorlayer, and including a select gate connected to the first other selectgate, the third connecting portion transistor being provided between thethird memory cell group and the third other select transistor, includinga channel formed in the third semiconductor layer, and including asecond connecting portion gate, the third other memory cell group beingprovided between the third other select transistor and the thirdconnecting portion transistor and including a plurality of third othermemory transistors connected in series, each of the plurality of thirdother memory transistors including a channel formed in the thirdsemiconductor layer, being electrically connected to the first othercontrol gate, and allowing data to be electrically rewritten, the firstwiring being connected to the first semiconductor layer on a side of thefirst select transistor opposite to the first memory cell group, andbeing connected to the second semiconductor layer on a side of thesecond select transistor opposite to the second memory cell group, thesecond wiring being connected to the third semiconductor layer on a sideof the third select transistor opposite to the third memory cell group,the first other wiring being connected to the first semiconductor layeron a side of the first other select transistor opposite to the firstother memory cell group, and being connected to the third semiconductorlayer on a side of the third other select transistor opposite to thethird other memory cell group, the second other wiring being connectedto the second semiconductor layer on a side of the second other selecttransistor opposite to the second other memory cell group, in aselective erase operation for performing at least one of injection of ahole into a charge retention layer of a selected cell transistor of thefirst memory transistors and extraction of an electron from the chargeretention layer, the control unit being configured to: apply a firstvoltage to the first wiring, apply a second voltage lower than the firstvoltage to a selected cell gate of the selected cell transistor, apply athird voltage not higher than the first voltage and higher than thesecond voltage to a non-selected cell gate of the first memorytransistors other than the selected cell transistor, apply a fourthvoltage not higher than the first voltage and not lower than the thirdvoltage to the first select gate, apply the second voltage or a fifthvoltage higher than the second voltage and not higher than the thirdvoltage to the second wiring, apply a sixth voltage lower than the thirdvoltage to the second control gate of the second memory transistors,apply a seventh voltage lower than the third voltage to the secondselect gate, apply the fifth voltage or the second voltage to the firstother wiring, apply the third voltage to the first other control gate,apply an eighth voltage lower than the third voltage to the first otherselect gate, apply a ninth voltage lower than the first voltage andhigher than the second voltage to the first connecting portion gate,apply the second voltage to the second other wiring, apply the sixthvoltage to the second control gate, apply the eighth voltage to thesecond select gate, and apply the eighth voltage to the second otherselect gate.
 22. A nonvolatile semiconductor memory device comprising: amemory array including a first memory string, the first memory stringincluding a first memory cell and a second memory cell, the first memorycell being provided at a first position of a first semiconductor layer,the second memory cell being provided at a second position of the firstsemiconductor layer, the first semiconductor layer extending in a firstdirection, an end of the first semiconductor layer being connected withan end of a second semiconductor layer extending in the first direction;a first wiring extending in a second direction crossing the firstdirection, the first wiring being connected with the first memory cell;a second wiring extending in the second direction, the second wiringbeing connected with the second memory cell; a first bit lineelectrically connected with the first semiconductor layer; a firstsource line electrically connected with the first semiconductor layer;and a control circuit configured to perform a selective erase operationto selectively erase the first memory cell without erasing the secondmemory cell by: applying a first voltage to the first bit line, applyinga second voltage to the first wiring, the second voltage being lowerthan the first voltage, applying a third voltage to the second wiring,the third voltage being higher than the second voltage, and applying afourth voltage to the first source line, the fourth voltage being higherthan the second voltage.
 23. The device according to claim 22, whereinthe third voltage is lower than the first voltage.
 24. The deviceaccording to claim 22, wherein the fourth voltage is equal to the firstvoltage.
 25. The device according to claim 22, further comprising: athird wiring extending in the second direction, the first memory stringfurther including a first transistor provided at the first semiconductorlayer, the first transistor being connected with one end of the firstmemory cell, and the third wiring being connected with the firsttransistor.
 26. The device according, to claim 25, wherein to performthe selective erase operation, the control circuit applies a fifthvoltage to the third wiring, the fifth voltage being lower than thefirst voltage.
 27. The device according to claim 26, wherein the fifthvoltage is higher than the second voltage.
 28. The device according toclaim 26, wherein the fifth voltage is equal to the third voltage. 29.The device according to claim 25, further comprising a fourth wiringextending in the second direction, the first memory string furtherincluding a second transistor provided at the first semiconductor layer,the second transistor being connected with one end of the first memorycell, and the fourth wiring being connected with the second transistor.30. The device according to claim 29, wherein to perform the selectiveerase operation, the control circuit applies a sixth voltage to thefourth wiring, the sixth voltage being lower than the first voltage. 31.The device according to claim 30, wherein the sixth voltage is higherthan the second voltage.
 32. The device according to claim 30, whereinthe sixth voltage is equal to the third voltage.
 33. The deviceaccording to claim 30, wherein the memory array further includes a thirdmemory string, the third memory string includes a fifth memory cell anda sixth memory cell, the fifth memory cell is provided at a fifthposition of a third semiconductor layer, the sixth memory cell isprovided at a sixth position of the third semiconductor layer, the thirdsemiconductor layer extends in the first direction, and the first bitline is further electrically connected with the third semiconductorlayer, and the first source line is further electrically connected withthe third semiconductor layer.
 34. The device according to claim 33,further comprising a fifth wiring connected with the fifth memory cell;and a sixth wiring connected with the sixth memory cell.
 35. The deviceaccording to claim 34, wherein to perform the selective erase operation,the control circuit applies a ninth voltage to the fifth wiring, theninth voltage being lower than the first voltage, and applies a tenthvoltage to the sixth wiring, the tenth voltage being lower than thefirst voltage.
 36. The device according to claim 35, wherein the ninthvoltage is equal to the tenth voltage.
 37. The device according to claim22, wherein the memory array further includes a second memory string,the second memory string includes a third memory cell and a fourthmemory cell, the third memory cell is provided at a third position ofthe second semiconductor layer, and the fourth memory cell is providedat a fourth position of the second semiconductor layer, the first wiringis further connected with the third memory cell, and the second wiringis further connected with the fourth memory cell.
 38. The deviceaccording to claim 37, further comprising: a second bit lineelectrically connected with the second memory string, wherein to performthe selective erase operation, the control circuit applies a seventhvoltage to the second bit line, the seventh voltage being higher thanthe second voltage and lower than the first voltage.
 39. The deviceaccording to claim 38, further comprising: a second source lineelectrically connected with the second semiconductor layer, wherein toperform the selective erase operation, the control circuit applies aneighth voltage to the second source line, the eighth voltage beinghigher than the second voltage and lower than the first voltage.
 40. Thedevice according to claim 39, wherein the seventh voltage is equal tothe eighth voltage.
 41. A nonvolatile semiconductor memory devicecomprising: a memory array including a first memory string, the firstmemory string including a first memory cell and a second memory cell,the first memory cell being provided at a first position of a firstsemiconductor layer, the second memory cell being provided at a secondposition of the first semiconductor layer, and the first semiconductorlayer extending in a first direction; a first wiring extending in asecond direction crossing the first direction, the first wiring beingconnected with the first memory cell; a second wiring extending in thesecond direction, the second wiring being connected with the second menucell; a first bit line electrically connected with the firstsemiconductor layer; a first source line electrically connected with thefirst semiconductor layer; and a control circuit configured to perform aselective erase operation to selectively erase the first memory cellwithout erasing the second memory cell by: applying a first voltage tothe first bit line, applying a second voltage to the first wiring, thesecond voltage being lower than the first voltage, applying a thirdvoltage to the second wiring, third voltage being higher than the secondvoltage, and applying a fourth voltage to the first source line in theerase operation, the fourth voltage being higher than the secondvoltage.